Computer Laboratory – Course pages 2015–16: Computer Design Skip to content | Access key help Search Advanced search A–Z Contact us Computer Laboratory Computer Laboratory Teaching Courses 2015–16 Computer Design Computer Design Computer Graphics and Image Processing Computer Networking Concurrent and Distributed Systems ECAD and Architecture Practical Classes Further Java Mathematical Methods for Computer Science Programming in C and C++ Prolog Semantics of Programming Languages Software Engineering Unix Tools Compiler Construction Computation Theory Databases Logic and Proof Artificial Intelligence I Complexity Theory Concepts in Programming Languages Economics, Law and Ethics Security I Course pages 2015–16 Computer Design Syllabus Course materials Information for supervisors Questions Principal lecturers: Prof Simon Moore, Dr Timothy Jones Taken by: Part IB Past exam questions No. of lectures: 18 (plus 4 via a web-based tutor) Suggested hours of supervisions: 5 Prerequisite course: Digital Electronics Companion course: Electronic Computer Aided Design (ECAD) This course is a prerequisite for the Part II courses Comparative Architectures and System-on-Chip Design. Aims The aims of this course are to introduce a hardware description language (SystemVerilog) and computer architecture concepts in order to design computer systems. The parallel ECAD+Arch practical classes will allow students to apply the concepts taught in lectures. The course starts with a web-based SystemVerilog tutor which is a prerequisite for the ECAD+Arch practical classes. There are then eighteen lectures in three six-lecture parts. Part 1 goes from gates to a simple processor. Part 2 looks at instruction set and computer architecture. Part 3 analyses the architecture of modern systems-on-chip. Lectures Part 0 - SystemVerilog Web tutor This web tutor is a prerequisite to starting the ECAD+Arch laboratory sessions [equivalent to approximately 4 lectures] Part 1 - Gates to processors [lecturer: Simon Moore] Introduction and motivation. [1 lecture] Current technology, technology trends, ECAD trends, challenges. Logic modelling, simulation and synthesis. [1 lecture] Logic value and delay modelling. Discrete event and device simulation. Automatic logic minimization. SystemVerilog FPGA design. [1 lecture] Practicalities of mapping SystemVerilog descriptions of hardware (including a processor) onto an FPGA board. Tips and pitfalls when generating larger modular designs. Chip, board and system testing. [1 lecture] Production testing, fault models, testability, fault coverage, scan path testing, simulation models. Building a simple computer. [2 lectures] Part 2 - Instruction sets and introduction to computer architecture [lecturer: Simon Moore] Historical perspective on computer architecture. [1 lecture] EDSAC versus Manchester Mark I. RISC machines. [1 lecture] Introduction to ARM and MIPS RISC processor designs. CISC and virtual machines [1 lecture] The Intel x86 instruction set and the Java Virtual Machine (JVM). Memory hierarchy. [1 lecture] Caching, etc. Hardware support for operating systems. [1 lecture] Memory protection, exceptions, interrupts, etc. Pipelining and data paths. [1 lecture] Part 3 - Systems-on-chip [lecturer: Timothy Jones] Overview of Systems-on-Chip (SoCs). [1 lecture] What are they and how do we program them? Multicore Processors. [2 lectures] Communication, cache coherence, barriers and synchronisation primitives Graphics processing units (GPUs) [2 lectures] Basic GPU architecture and programming Future Directions [1 lecture] Where is computer architecture heading? Objectives At the end of the course students should be able to read assembler given a guide to the instruction set and be able to write short pieces of assembler if given an instruction set or asked to invent an instruction set; understand the differences between RISC and CISC assembler; understand what facilities a processor provides to support operating systems, from memory management to software interrupts; understand memory hierarchy including different cache structures and coherency needed for multicore systems; understand how to implement a processor in SystemVerilog; appreciate the use of pipelining in processor design; have an appreciation of control structures used in processor design; have an appreciation of system-on-chip design. Recommended reading * Harris, D.M. & Harris, S.L. (2007). Digital design and computer architecture: from gates to processors. Morgan Kaufmann. Recommended further reading: Hennessy, J. & Patterson, D. (2006). Computer architecture: a quantitative approach. Elsevier (4th ed.). ISBN 978-0-12-370490-0. (Older versions of the book are also still generally relevant.) Patterson, D.A. & Hennessy, J.L. (2004). Computer organization and design. Morgan Kaufmann (3rd ed., as an alternative to the above). (2nd ed., 1998, is also good.) Pointers to sources of more specialist information are included in the lecture notes and on the associated course web page. © 2016 Computer Laboratory, University of Cambridge Information provided by Prof Simon Moore
