Computer Laboratory – Course pages 2016–17: ECAD and Architecture Practical Classes - Lab 2 -
FPGA synthesis Skip to content | Access key help Search Advanced search A–Z Contact us Computer Laboratory Computer Laboratory Teaching Courses 2016–17 ECAD and Architecture Practical Classes Exercise 6 Computer Design Computer Graphics and Image Processing Computer Networking Concurrent and Distributed Systems ECAD and Architecture Practical Classes Further Java Mathematical Methods for Computer Science Programming in C and C++ Prolog Semantics of Programming Languages Software Engineering Unix Tools Compiler Construction Computation Theory Databases Logic and Proof Artificial Intelligence I Complexity Theory Concepts in Programming Languages Economics, Law and Ethics Security I Course pages 2016–17 ECAD and Architecture Practical Classes Syllabus Course outline Pre-lab setup Workflow Exercise 0 Exercise 1 FPGA intro Exercise 2a Qsys / Ex 2b Optional A* Clarvi / Ex 3 Tick 1 Exercise 4 Clarvi on FPGA Exercise 6 Tick 2 Downloads & ticklist Additional material Exercise 6: Etch-a-sketch (or Pong) on FPGA Adding your Verilog components Now is time to add your rotary controllers and shift register to your Qsys project, so we can access them from Clarvi. From Exercise 5, copy the Verilog for the rotary encoders and shift register into your clarvi_fpga folder. Also copy the files ending _hw.tcl - these are the defintions for your Qsys components. Start Qsys and open clarvi_soc.qsys. If you have Qsys already open, go to File | Refresh System (or press F5) to cause Qsys to rescan and add them to its library of components. In Qsys you should see the rotary encoder (and shift register if you made a Qsys component) appear as components in the IP Catalog on the left. You can double click to add one instance to your design. Add a rotary controller and move it next to your leftdial_pio with the up/down buttons on the toolbar. Connect up the clock and reset as your other components. Export the rotary_in and rotary_event ports of the rotary controller. Finally join the rotary_pos output port of the rotary controller to the external_connection of the leftdial_pio. Add a second rotary controller and connect it to the rightdial_pio. Add the shift register Qsys component and connect it to the buttons_pio. Your system should like similar to the image below: We have now finished adding hardware to the system so we can generate the system. Before doing so, go to Generate | Instantiation Template and copy the code to instantiate the Qsys project in your top level Verilog. Then you can Generate HDL... While it is generating, go back to Quartus and open toplevel.sv. Using the code you copied, adjust the instantiation of the Qsys project to add any extra ports that are now present on the Qsys project (it is probably safer to cut and paste ports into the existing declaration than paste in a complete new declaration from scratch - making an error with the memory or reset connections can be time consuming to debug). Wire the ports from the Qsys instantiation as follows (your names may be slightly different): Qsys port I/O pin rotaryctl_left_rotary_in_rotary_in DIALL rotaryctl_left_rotary_event_cw Don't connect rotaryctl_left_rotary_event_ccw Don't connect rotaryctl_right_rotary_in_rotary_in DIALR rotaryctl_right_rotary_event_cw Don't connect rotaryctl_right_rotary_event_ccw Don't connect shiftregctl_0_shiftreg_port_shiftreg_loadn SHIFT_LOAD shiftregctl_0_shiftreg_port_shiftreg_out SHIFT_OUT shiftreglct_0_shiftreg_port_shiftreg_clk SHIFT_CLKIN Adding your software and building the FPGA Find the path of your Etch A Sketch or Pong code in relation to your clarvi_fpga directory, for example ../../exercise4/software. When in your clarvi_fpga directory, change the symlink to point to its mem.hex: rm mem.hex
ln -s ../../exercise4/software/build/mem.hex mem.hex
and check this symlink works. Check your software builds correctly, and then it is time to start your FPGA synthesis. While it is building, have a look at the questions for Tick 2. When your build has completed, download to your FPGA and test your code. © 2016 Computer Laboratory, University of Cambridge Information provided by Prof Simon Moore
