Computer Laboratory – Course pages 2016–17 (still under preparation!): ECAD and Architecture Practical Classes – Course materials Skip to content | Access key help Search Advanced search A–Z Contact us Computer Laboratory Computer Laboratory Teaching Courses 2016–17 ECAD and Architecture Practical Classes Course outline Computer Design Computer Graphics and Image Processing Computer Networking Concurrent and Distributed Systems ECAD and Architecture Practical Classes Further Java Mathematical Methods for Computer Science Programming in C and C++ Prolog Semantics of Programming Languages Software Engineering Unix Tools Compiler Construction Computation Theory Databases Logic and Proof Artificial Intelligence I Complexity Theory Concepts in Programming Languages Economics, Law and Ethics Security I Course pages 2016–17 (still under preparation!) ECAD and Architecture Practical Classes Syllabus Course outline Pre-lab setup Workflow Exercise 0 Exercise 1 FPGA intro Exercise 2a Qsys / Ex 2b Optional A* Clarvi / Ex 3 Tick 1 Exercise 4 Clarvi on FPGA Exercise 6 Tick 2 Downloads & ticklist Additional material Introduction The ECAD and Architecture Laboratory sessions are a companion to the Computer Design course. The objective is to provide experience of hardware design for FPGA including use of a small embedded processor. Laboratory sessions are timetabled for Tuesday and Friday afternoons. You will sign up for either Tuesday or Friday and you should stick to your slot – we do not have enough capacity to handle more than half the class on a given day. Laboratory sessions are times when you can get expert help and have your work assessed; this is not necessarily the time when you need to complete the work since you can work in other locations. We will allocate hardware to students for the duration of the laboratory sessions (i.e. you get your own kit). Last year we introduced new hardware and laboratory sessions and we have made many refinements for this year. Please be patient of bugs in the new laboratories and the creators (Simon Moore and Theo Markettos) appreciate constructive feedback. Assessment There are two ticked exercises with each exercise broken up into smaller, more manageable chunks. Ticks are awarded after demonstrating a working system to a laboratory assessor, and will be awarded during lab time (i.e. until the end of Week 8). Even if you work at home, you will still need to attend some lab sessions for ticking and for demonstrator help: do not assume you can complete the tick work entirely on your own. Speak to a demonstrator if you are having difficulties with the ticked material. Code created must be submitted as a portfolio of work by early Lent term (see the Head of Department Notices for the definitive date). Laboratory Exercises If you have a suitable laptop we strongly recommend using the ECAD tools in a virtual machine, which will enable you to complete the labs in less time than using the computers in the Intel Lab. Follow the pre-lab setup guide before you arrive for your first session to ensure you have downloaded and configured the virtual machine. Exercise 0: SystemVerilog web tutor - learn more about SystemVerilog by completing all of our web tutor before starting ticked laboratory sessions. Exercise 1: Inputs to the DE1-SoC board - write SystemVerilog to interact with physical inputs to the FPGA and test in simulation. Exercise 2: Introduction to FPGA synthesis and the Altera Quartus and Qsys tools Optional exercise A: Audio generator in Qsys Exercise 3: The Clarvi RISC-V processor Exercise 4: Etch-A-Sketch on Clarvi in simulation Exercise 5: Clarvi on FPGA Exercise 5: Etch-A-Sketch in hardware on the FPGA Laboratory Signup Sign-up for the ECAD+Arch Laboratories at the first Computer Design lecture. © 2016 Computer Laboratory, University of Cambridge Information provided by Prof Simon Moore
