Basic MIPS Instructions sections in this module City College of San Francisco - CS270 Computer Architecture Module: MIPS-I module list Basic MIPS Instructions MIPS, which was an acronym for Microprocessor without Interlocking Pipe Stages, was a very successful microprocessor in the 1990s. Over time it was unable to compete with the resources thrown at the Intel family in the PC business or with the success of the ARM chips in the mobile phone devices, but it has carved out a solid niche in the embedded market - routers, cable modems, set-top boxes, and gaming consoles such as the PlayStation II. Its main advantages are its relatively simple (and regular) instruction set, and its low cost and low power requirements. The regular (though complete) instruction set is the main reason MIPS processors are used in Computer Architecture courses. It helps that the definitive work on the topic was written by the original proponent of the architecture at Stanford University in the late 1980s and early 1990s. MIPS was revolutionary for its time. It was probably the chip that settled the longstanding competition between RISC chips and the then-dominant CISC chips. All new microprocessor chips made today are RISC. The only surviving CISC chip in use is the Intel family, and it could be argued that it is only Intel's Herculean effort and resources (and their large installed base) that has kept this technology in the forefront. The MIPS instruction set is easier to program, use, and implement for several reasons every instruction is a standard length - for our family, 32 bits. there is a large number (32) of uniform registers. For 31 of these registers their use is restricted only by convention. (But in reality only 26 registers are generally available) there are very few different instruction encodings there are no condition codes it can function in either big- or little-endian mode the procedure calling convention is lightweight, enabling simple leaf procedures to be called with very little overhead the assembly language is easily optimized and its regularity (and large number of registers) makes "smart" compilers easier to write. (In fact, early MIPS chips relied on the compiler to generate code in a special way to avoid the necessity of pipeline interlocks, hence its acronym) MIPS future was in question several times over its history. As recently as ten years ago it seemed destined for limited use in embedded devices. Since then, however, a huge investment has been made in enhancing and licensing the technology from various sources, culminating in the purchase of the company itself by a Chinese consortium a few years ago. This was preceded by many years of independent development of MIPS-based processors (named Gobson and Loongson. It was at that time on the short list of processors being considered to be chosen for a national Chinese architecture. It is curious that the company was purchased (thus alleviating any outstanding patent issues) soon afterwards. The winner of the national architecture was never announced in the media. You can read a lot of details about the status of the various Chinese MIPS processors on wikipedia here. MIPS parameters All MIPS instructions are 32-bits. To ease the writing of assembly instructions given this restriction, the MIPS assembler allows pseudoinstructions, which appear to be simple instructions, but, instead generate a sequence of up to three actual MIPS instructions. To facilitate the use of pseudoinstructions, register 1 ($1 or $at) is reserved as the assembler temporary. All operations are performed in registers on 32-bit quantities. The only instructions that access memory are loads and stores, and these are the only instructions that indicate data size. Loads and stores must be properly aligned. Thus a load of a four-byte quantity must be done from an address that is a multiple of four. Loads of small sizes (halfword or byte) have signed and unsigned versions. Register classes As indicated, MIPS has a convention for register usage. Registers are divided into register classes: special-use. These registers are reserved for a special purpose. This includes $0, $at, $v0/$v1 (function result), the stack, frame, and global pointer registers, the return address register, and the two kernel registers (10 total). Except for the kernel registers, the stack pointer, and $0, you may use these registers for other uses if you obey the rules. $a0-$a3 are argument registers. We will discuss them later. $s0-$s7 are "saved" registers. These are usually used to "hold" a value for a long period of time. Again, later. $t0-$t9 are "temporary" registers. Use these registers for calculations. Basic instruction encoding. MIPS instructions are divided into fields, just like our Simple Machine. The fields indicate the operation, and the operands. Let's take this a step at a time the operation, strangely, is split into two fields - the opcode field and, in some instructions, the function field, each 6 bits wide. The opcode field comprises the most-significant bits of the instruction. The function field comprises the least-significant part. Basically this design "moves" the indication of the operation between the two fields based on which instruction encoding is used, as we will see. every instruction has space for two registers, each encoded in 5 bits. some instructions have space for a third register, a shift field, and the optional function field. Other instructions use this space for a 16-bit constant. Let's see how this works: Arithmetic Instructions Arithmetic instructions are encoded as R-type instructions. They have the following parts an opcode field that basically says the opcode is in the function field instead. two source registers (rs and rt) a destination register (rd) an optional 5 bit shift amount (for shift instructions) They are used, of course, for arithmetic operations such as add, shift, and, and or. (Note that the use of the registers changes in the shift instructions. See below.) Examples: add rd,rs,rt # rd = rs + rt (signed addition. overflow is possible) addu rd,rs,rt # rd = rs + rt (unsigned addition) and rd,rs,rt # rd = rs AND rt sll rd,rt, N # rd = rt << N (0
