Java程序辅导
C C++ Java Python Processing编程在线培训 程序编写 软件开发 视频讲解
C C++ Java Python Processing编程在线培训 程序编写 软件开发 视频讲解
MIPS Instructions 1. Arithmetic and Logical Instructions 2. Constant-Manipulating Instructions 3. Comparison Instructions 4. Branch Instructions 5. Store Instructions 6. Load Instructions 7. Data Movement Instructions 8. Quick Reference 1. Arithmetic Instructions: add, sub Name Op-Code Dest Src1 Src2 Addition (with overflow) add rd, rs, rt Addition (without overflow) addu rd, rs, rt Addition immediate addi rt, rs, imm (with overflow) Addition immediate addiu rt rs imm (without overflow) Name Op-Code Dest Src1 Src2 Subtract (with overfl ow) sub rd, rs, rt Subtract (without overflow) subu rd, rs, rt Arithmetic Instruction: div Name Op-Code Dest Src1 Src2 Divide (with overflow) div rs, rt Divide (without overflow) divu rs, rt Divide register rs by register rt. • the quotient is in register lo and, • the remainder is in register hi. Note that if an operand is negative, the remainder is unspecified by the MIPS architecture and depends on the convention of the machine on which SPIM is run. Arithmetic Instructions: mult, mul Name Op-Code Dest Src1 Src2 Multiply mult rs, rt Unsigned multiply multu rs, rt Multiply registers rs and rt. • the low-order word of the product in register lo and • the high-order word in register hi. Name Op-Code Dest Src1 Src2 Multiply (without overflow) mul rd, rs, rt Take the low-order 32 bits of the product Arithmetic Pseudo-Instructions Name Op-Code Dest Src1 Src2 Absolute value abs rdest, rsrc Divide (with overflow) div rdest, rsrc1, src2 Divide (without overflow) divu rdest, rsrc1, src2 Multiply (without overflow) mul rdest, rsrc1, src2 Multiply (with overflow) mulo rdest, rsrc1, src2 Unsigned multiply (with overflow) mulou rdest, rsrc1, src2 Negate value (with overflow) neg rdest, rsrc Negate value (without overflow) negu rdest, rsrc Name Op-Code Dest Src1 Src2 Remainder rem rdest, rsrc1, rsrc2 Unsigned remainder remu rdest, rsrc1, rsrc2 Shift Instructions: sll, sra, srl Name Op-Code Dest Src1 Src2 Shift left logical sll rd, rt, shamt Shift left logical variable sllv rd, rt, rs Shift right arithmetic sra rd, rt, shamt Shift right arithmetic variable srav rd, rt, rs Shift right logical srl rd, rt, shamt Shift right logical variable srlv rd, rt, rs Shift register rt left (right) by the distance indicated by immediate shamt or the register rs and put the result in register rd. Note: What is difference between shift-right logical and shift-right arithmetic? Rotation Pseudo-Instructions: rol, ror Name Op-Code Dest Src1 Src2 Rotate left rol rdest, rsrc1, rsrc2 Rotate right ror rdest, rsrc1, rsrc2 Rotate register rsrc1 left (right) by the distance indicated by rsrc2 and put the result in register rdest. Logical Instructions: and, nor, or, xor Name Op-Code Dest Src1 Src2 AND and rd, rs, rt AND immediate andi rd, rs, imm NOR nor rd, rs, rt NOT* not rdest, rsrc OR or rd, rs, rt OR immediate ori rt, rs, imm Exclusive OR xor rd, rs, rt XOR immediate xori rt, rs, imm * This is a pseudo-instruction. 2. Constant-Manipulating Instructions Name Op-Code Dest Src1 Src2 Load upper immediate lui rt, imm Load the lower halfword of the immediate imm into the upper halfword of register rt. The lower bits of the register are set to 0. Name Op-Code Dest Src1 Src2 Load immediate* li rdest, imm * This is a pseudo-instruction. 3. Comparison Instructions Name Op-Code Dest Src1 Src2 Set less than slt rd, rs, rt Set less than unsigned sltu rd, rs, rt Set less than immediate slti rt, rs, imm Set less than unsigned immediate sltiu rt, rs, imm Set equal* seq rdest, rsrc1, rsrc2 Set greater than equal* sge rdest, rsrc1, rsrc2 Set greater than equal unsigned sgeu rdest, rsrc1, rsrc2 Set greater than* sgt rdest, rsrc1, rsrc2 Set greater than unsigned* sgtu rdest, rsrc1, rsrc2 Set less than equal* sle rdest, rsrc1, rsrc2 Set less than equal unsigned* sleu rdest, rsrc1, rsrc2 Set not equal* sne rdest, rsrc1, rsrc2 * This is a pseudo-instruction. 4. Branch Instructions Name Op-Code Src1 Src2 Dest Branch on equal beq rs, rt, label Branch on greater than equal zero bgez rs, label Branch on greater than zero bgtz rs, label Branch on less than equal zero blez rs, label Branch on not equal bne rs, rt, label Conditionally branch the number of instructions specified by the offset. That is PC+ 4 + (Offset × 4) Branch Pseudo-Instructions Name Op-Code Src1 Src2 Dest Branch b label Branch on equal zero beqz rsrc, label Branch on greater than equal bge rsrc1, rsrc2, label Branch on greater than equal bgeu rsrc1, rsrc2, label unsigned Branch on greater than bgt rsrc1, src2, label Branch on greater than unsigned bgtu rsrc1, src2, label Branch on less than equal ble rsrc1, src2, label Branch on less than equal bleu rsrc1, src2, label unsigned Branch on less than blt rsrc1, rsrc2, label Branch on less than unsigned bltu rsrc1, rsrc2, label Branch on not equal zero bnez rsrc, label Jump Instructions Name Op-Code Dest Jump j target Unconditionally jump to the instruction at target × 4. Save the address of the next instruction in register $ra. Unconditionally jump to the instruction at target × 4. Name Op-Code Dest Jump and link jal target 5. Store Instructions: sb, sh, sw Name Op-Code Targ Address Store byte sb rt, offset(rs) Store halfword sh rt, offset(rs) Store word sw rt, offset(rs) Store the low byte from register rt at address = rs + offset Store the low halfword from register rt at address = rs + offset Store the word from register rt at address = rs + offset 6. Load Instructions: la, lb Name Op-Code Dest Address Load address* la rdest, label Load computed address of the label location—not the contents of the location—into register rdest. Name Op-Code Targ Address Load byte lb rt, offset(rs) Load unsigned byte lbu rt, offset(rs) Load the byte at address = rs + offset into register rt. The byte is sign-extended by lb, but not by lbu. Load Instructions: lh, lw Name Op-Code Targ Address Load word lw rt, offset(rs) Load the 32-bit quantity (word )at address = rs + offset into register rt. Name Op-Code Targ Address Load halfword lh rt, offset(rs) Load unsigned halfword lhu rt, offset(rs) Load the 16-bit quantity (halfword) at address = rs + offset into register rt. The halfword is sign-extended by lh, but not by lhu. 7. Data Movement Instructions: move Name Op-Code Dest Src Comment Move * move rdest, rsrc # rdest = rsrc Move from hi mfhi rd # rd = hi Move from lo mflo rd # rd = lo Move to hi mthi rs # hi = rs Move to lo mtlo rs # lo = rs * This is a pseudo-instruction. 8. Quick Reference: Instructions Integer Instruction Set Name opcode Oprand Add: add Rd, Rs, Rt Add Immediate: addi Rt, Rs, Imm Add Immediate Unsigned: addiu Rt, Rs, Imm Add Unsigned: addu Rd, Rs, Rt And: and Rd, Rs, Rt And Immediate: andi Rt, Rs, Imm Branch if Equal: beq Rs, Rt, Label Branch if Greater Than or Equal to Zero: bgez Rs, Label Branch if Greater Than or Equal to Zero and Link: bgezal Rs, Label Branch if Greater Than Zero: bgtz Rs, Label Branch if Less Than or Equal to Zero: blez Rs, Label Branch if Less Than Zero and Link: bltzal Rs, Label Branch if Less Than Zero: bltz Rs, Label Branch if Not Equal: bne Rs, Rt, Label Divide: div Rs, Rt Divide Unsigned: divu Rs, Rt Jump: j Label Jump and Link: jal Label Integer Instruction Set Name Opcode Operand Jump and Link Register: jalr Rd, Rs Jump Register: jr Rs Load Byte: lb Rt, offset(Rs) Load Byte Unsigned: lbu Rt, offset(Rs) Load Halfword: lh Rt, offset(Rs) Load Halfword Unsigned: lhu Rt, offset(Rs) Load Upper Immediate: lui Rt, Imm Load Word: lw Rt, offset(Rs) Load Word Left: lwl Rt, offset(Rs) Load Word Right: lwr Rt, offset(Rs) Move From Coprocessor 0 mfc0 Rd, Cs Move From High: mfhi Rd Move From Low: mflo Rd Move To Coprocessor 0 mtc0 Rt, Cd Move to High: mthi Rs Move to Low: mtlo Rs Multiply: mult Rs, Rt Multiply Unsigned: multu Rs, Rt NOR: nor Rd, Rs, Rt OR: or Rd, Rs, Rt OR Immediate: ori Rt, Rs, Imm Return From Exception: rfe Integer Instruction Set Name Opcode Operand Store Byte: sb Rt, offset(Rs) Store Halfword: sh Rt, offset(Rs) Shift Left Logical: sll Rd, Rt, sa Shift Left Logical Variable: sllv Rd, Rt, Rs Set on Less Than: slt Rd, Rt, Rs Set on Less Than Immediate: slti Rt, Rs, Imm Set on Less Than Immediate Unsigned: sltiu Rt, Rs, Imm Set on Less Than Unsigned: sltu Rd, Rt, Rs Shift Right Arithmetic: sra Rd, Rt, sa Shift Right Arithmetic Variable: srav Rd, Rt, Rs Shift Right Logical: srl Rd, Rt, sa Shift Right Logical Variable: srlv Rd, Rt, Rs Subtract: sub Rd, Rs, Rt Subtract Unsigned: subu Rd, Rs, Rt Store Word: sw Rt, offset(Rs) Store Word Left: swl Rt, offset(Rs) Store Right: swr Rt, offset(Rs) System Call: syscall Exclusive OR: xor Rd, Rs, Rt Exclusive OR Immediate: xori Rt, Rs, Imm Quick Reference: PseudoInstructions Integer Instruction Set Name opcode Oprand Absolute value abs rdest, rsrc Branch b label Branch on equal zero beqz rsrc, label Branch on greater than equal bge rsrc1, rsrc2, label Branch on greater than equal unsigned bgeu rsrc1, rsrc2, label Branch on greater than bgt rsrc1, src2, label Branch on greater than unsigned bgtu rsrc1, src2, label Branch on less than equal ble rsrc1, src2, label Branch on less than equal unsigned bleu rsrc1, src2, label Branch on less than blt rsrc1, rsrc2, label Branch on less than unsigned bltu rsrc1, rsrc2, label Branch on not equal zero bnez rsrc, label Divide (with overflow) div rdest, rsrc1, src2 Divide (without overflow) divu rdest, rsrc1, src2 Move * move rdest, rsrc Integer Instruction Set Name opcode Oprand______ Multiply (without overflow) mul rdest, rsrc1, src2 Multiply (with overflow) mulo rdest, rsrc1, src2 Unsigned multiply (with overflow) mulou rdest, rsrc1, src2 Load address* la rdest, label Load immediate* li rdest, imm Negate value (with overflow) neg rdest, rsrc Negate value (without overflow) negu rdest, rsrc NOT* not rdest, rsrc Rotate left rol rdest, rsrc1, rsrc2 Rotate right ror rdest, rsrc1, rsrc2 Set equal* seq rdest, rsrc1, rsrc2 Set greater than equal* sge rdest, rsrc1, rsrc2 Set greater than equal unsigned sgeu rdest, rsrc1, rsrc2 Set greater than* sgt rdest, rsrc1, rsrc2 Set greater than unsigned* sgtu rdest, rsrc1, rsrc2 Set less than equal* sle rdest, rsrc1, rsrc2 Set less than equal unsigned* sleu rdest, rsrc1, rsrc2 Set not equal* sne rdest, rsrc1, rsrc2