Research: Profile-Driven Parallelisation University Homepage School Homepage School Contacts School Search Institute for Computing Systems Architecture Profile-Driven Parallelisation Compiler-based auto-parallelization is a much studied area, yet has still not found wide-spread application. This is largely due to the poor exploitation of application parallelism, subsequently resulting in performance levels far below those which a skilled expert programmer could achieve. We have identified two weaknesses in traditional parallelizing compilers and propose a novel, integrated approach, resulting in significant performance improvements of the generated parallel code. Using profile-driven parallelism detection we overcome the limitations of static analysis, enabling us to identify more application parallelism and only rely on the user for final approval. In addition, we replace the traditional target-specific and inflexible mapping heuristics with a machine-learning based prediction mechanism, resulting in better mapping decisions while providing more scope for adaptation to different target architectures. We have evaluated our parallelization strategy against the NAS and SPEC OMP benchmarks and two different multi-core platforms (dual quad-core Intel Xeon SMP and dual-socket QS20 Cell blade). We demonstrate that our approach not only yields significant improvements when compared with state-of-the-art parallelizing compilers, but comes close to and sometimes exceeds the performance of manually parallelized codes. On average, our methodology achieves 96% of the performance of the hand-tuned OpenMP NAS and SPEC parallel benchmarks on the Intel Xeon platform and gains a significant speedup for the IBM Cell platform, demonstrating the potential of profile-guided and machine-learning based parallelization for complex multi-core platforms. Publications G.Tournavitis, Z.Wang, B.Franke and M.O'Boyle Towards a Holistic Approach to Auto-Parallelization: Integrating Profile-Driven Parallelism Detection and Machine-Learning Based Mapping ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI'09), Dublin, Ireland, June 15. G.Tournavitis and B.Franke Towards Automatic Profile-Driven Parallelization of Embedded Multimedia Applications Second Workshop on Programmability Issues for Multi-Core Computers (MULTIPROG'09), Paphos, Cyprus, January 25. Search... Home News Publications Posters Press People Seminars Contact Internal PASTA Activities EnCore Tools ECC Compiler GCC Compiler ArcSim Simulator Verification/Co-Simulation HW Systems EnCore Processor EnCore Calton EnCore Castle FPGA Platform ASIC Flow Chips & Boards M.Sc. and UG Projects Research Areas Resource Sharing Configurable Flow Accelerators Automated ISE Mapping ISE Power Prediction & Optimisation Interconnect Synthesis Cache Optimisation for Embedded Systems Compilation for Dual Memory Banks Fast Cycle-Approximate Simulation High-Speed Simulation Profile-Driven Parallelisation Unless explicitly stated otherwise, all material is copyright © The University of Edinburgh.
