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Computer Architecture (E Edwards) 8.1 CPU Organisation & Operation Eddie Edwards eedwards@doc.ic.ac.uk https://www.doc.ic.ac.uk/~eedwards/compsys/ Heavily based on notes by Naranker Dulay Computer Architecture (E Edwards) 8.2 Composition of a CPU Computer Architecture (E Edwards) 8.3 Composition of a CPU Control Unit Generated control/timing signals Controls decoding/execution of instruction Arithmetic Logic Unit (ALU) Used during execution of instructions Performs mathematical operations (* / + - etc.) Also logical operations, and/or etc. and also shift/rotate Registers Program counter (address of next instruction) Instruction register (holds current instruction) Stack Pointer (address of top of stack) Accumulator (holds result of ALU operations) General purpose registers (hold intermediate results or addresses during instructions) Computer Architecture (E Edwards) 8.4 Simple CPU Computer Architecture (E Edwards) 8.5 Fetch-Execute Cycle Fetch the Instruction Increment the Program Counter Decode the Instruction Fetch the Operands Perform the Operation Store the Results Repeat Forever Computer Architecture (E Edwards) 8.6 Animated CPU example See http://www.doc.ic.ac.uk/~eedwards/compsys/cpu/iecycle.swf Computer Architecture (E Edwards) 8.7 High-Level/Low-Level Languages, Machine Code High-Level Language (e.g. Java, C++, Haskell) A = B + C Assignment Statement Low-Level Language -> Assembly Language (e.g. Pentium, PowerPC, ARM etc, Java Bytecode) LOAD R2, B Assembly Language ADD R2, C Instructions STORE R2, A (Binary) Machine Code 0001101000000001 Machine Code 0011101000000010 Instructions 0010101000000000 Computer Architecture (E Edwards) 8.8 The Toy1 Architecture Maximum of 1024 x 16-bit memory words Memory is Word Addressed Two’s Complement Integer Representation 4 General Purpose Registers (16-bit) : R0, R1, R2, R3 Upto 16 “Instructions”, e.g. LOAD, ADD, STORE Computer Architecture (E Edwards) 8.9 Toy1 Instruction Set LOAD Register , [MemoryAddress] Register = Memory [MemoryAddress] STORE Register , [MemoryAddress] Memory [MemoryAddress] = Register ADD Register , [MemoryAddress] Register = Register + Memory [MemoryAddress] SUB Register , [MemoryAddress] Register = Register - Memory [MemoryAddress] Computer Architecture (E Edwards) 8.10 Toy1 Instruction Format 4-bit OPCODE 2-bit REG 10-bit ADDRESS Instruction Fields OPeration CODE (Selects CPU Instruction) REGister (Specifies 1st Operand for Instruction) ADDRESS (Specifies 2nd Operand for Instruction) Machine Code ADD R2, CAssembly Instruction e.g. Computer Architecture (E Edwards) 8.11 Other Possibilities for the Format ADD R2, C 4-bit 2-bit10-bit OPCODE REGADDRESS 4-bit2-bit 10-bit OPCODEREG ADDRESS ADD R2, R3 REG 4-bit 2-bit OPCODE REG 2-bit 4-bit 2-bit OPCODE REG 2-bit REG Computer Architecture (E Edwards) 8.12 Instruction Field Encoding OPCODE LOAD 0001 (4-bit) STORE 0010 ADD 0011 SUB 0100 REG Register 0 00 (2-bit) Register 1 01 Register 2 10 Register 3 11 ADDRESS 10-bit Memory Word Address 4-bit 2-bit 10-bit OPCODE REG ADDRESS 16-bit Instruction Computer Architecture (E Edwards) 8.13 Memory Placement (Program) LOAD R2, [201H] 0001 10 10 0000 0001 00 1000 0000 A 0 1 1 ADD R2, [202H] 0011 10 10 0000 0010 A 0 2 3 00 1000 0001 0 8 1 H STORE R2, [200H] 0010 10 10 0000 0000 A 0 0 2 00 1000 0010 0 8 2 H Assembly Instruction Machine Instruction OP REG ADDRESS 0 8 0 H Memory Address MEMORY Computer Architecture (E Edwards) 8.14 Assembly Instruction Data Memory Address MEMORY Memory Placement (Data) A = 0 0000 0000 0000 0000 0 0 0 0 10 0000 0000 2 0 0 H B = 9 10 0000 0001 2 0 1 H C = 6 10 0000 0010 2 0 2 H 0000 0000 0000 1001 0 0 0 9 0000 0000 0000 0110 0 0 0 6 Computer Architecture (E Edwards) 8.15 CPU ALU RAM CPU Organisation R0 R1 R2 R3 Program Counter Instr. Register I n t e r n a l B u s 000 001 002 003 3FD 3FE 3FF Output Reg Input Reg1 Input Reg2 Instr. Decoder Control Unit Address Bus Data Bus Control Bus Computer Architecture (E Edwards) 8.16 CPU ALU RAM LOAD R2, [201H] R2=Memory[201H] 000 001 002 003 3FD 3FE 3FF Instr. Decoder Control Unit 080H 0 8 0 H 080H 080H 0 0 0 1 R2 PC Computer Architecture (E Edwards) 8.17 CPU ALU RAM LOAD R2, [201H] R2=Memory[201H] 000 001 002 003 3FD 3FE 3FF Instr. Decoder Control Unit 080H 080H 0 2 R2 PC + 1 Computer Architecture (E Edwards) 8.18 CPU ALU RAM LOAD R2, [201H] R2=Memory[201H] 000 001 002 003 3FD 3FE 3FF Instr. Decoder Control Unit 081H 080H 0 3 R2 PC Computer Architecture (E Edwards) 8.19 CPU ALU RAM LOAD R2, [201H] R2=Memory[201H] 000 001 3FD 3FE 3FF Instr. Decoder Control Unit 081H 080H 0 4 1A01 3A02H 2A00H 0000 0009 0006 080 081 082 200 201 202 R2 PC 1A01H Computer Architecture (E Edwards) 8.20 CPU ALU 1A01H 3A02H 2A00H 0000 0009 0006 RAM LOAD R2, [201H] R2=Memory[201H] 000 001 3FD 3FE 3FF 081H 5 080 081 082 200 201 202 1A01 1A01H 1 A 0 1 H 1A01H 1A01H1A01H 1, 2, 201H 1, 2, 201H 201H 2 0 1 H 201H 0 0 0 R2 PC Computer Architecture (E Edwards) 8.21 CPU ALU 1A01H 3A02H 2A00H 0000 0009 0006 RAM LOAD R2, [201H] R2=Memory[201H] 000 001 3FD 3FE 3FF 081H 6 080 081 082 200 201 202 00090009 0009 1A01H 1, 2, 201H 0 0 0 9 201H 0 201H 0 0009R2 PC Computer Architecture (E Edwards) 8.22 CPU ALU 1A01H 3A02H 2A00H 0000 0009 0006 RAM ADD R2, [202H] R2=R2+Memory[202H] 000 001 3FD 3FE 3FF 081H 7 080 081 082 200 201 202 081H 0 8 1 H 0009R2 PC 081H 0 0 0 Computer Architecture (E Edwards) 8.23 CPU ALU 1A01H 3A02H 2A00H 0000 0009 0006 RAM ADD R2, [202H] R2=R2+Memory[202H] 000 001 3FD 3FE 3FF 8 080 081 082 200 201 202081H 081H 0 0009R2 PC + 1 Computer Architecture (E Edwards) 8.24 CPU ALU 1A01H 3A02 2A00H 0000 0009 0006 RAM ADD R2, [202H] R2=R2+Memory[202H] 000 001 3FD 3FE 3FF 9 080 081 082 200 201 202 3A02H 082H 081H 0 0009R2 PC 3A02H 3 A 0 2 H 3A02H 3A02H3A02H 3, 2, 202H 3, 2, 202H 202H 2 0 2 H 202H 0 0 3A02H 0009 0 0 0 9 0009 0009 0 9 0 Computer Architecture (E Edwards) 8.25 CPU ALU 1A01 3A02 2A00 0000 0009 0006 RAM ADD R2, [202H] R2=R2+Memory[202H] 000 001 3FD 3FE 3FF 10 080 081 082 200 201 202 0006 082H 202H 0 0009R2 PC 0006 0006 3A02H 3, 2, 202H 202H 0 0006 ADD000FH 000FH 0 0 0 F H 000FH 000FH 0009 0 0 0 F H Computer Architecture (E Edwards) 8.26 CPU ALU 1A01H 3A02H 2A00H 0000 0009 0006 RAM STORE R2, [200H] Memory[200H]=R2 000 001 3FD 3FE 3FF 082H 11 080 081 082 200 201 202 082H 0 8 2 H 000FHR2 PC 082H 0 0 0 Computer Architecture (E Edwards) 8.27 CPU ALU 1A01H 3A02H 2A00H 0000 0009 0006 RAM 000 001 3FD 3FE 3FF 12 080 081 082 200 201 202082H 082H 0 000FHR2 PC + 1 STORE R2, [200H] Memory[200H]=R2 Computer Architecture (E Edwards) 8.28 CPU ALU 1A01H 3A02H 2A00 0000 0009 0006 RAM 000 001 3FD 3FE 3FF 13 080 081 082 200 201 202 2A00H 083H 082H 1 000FR2 PC 000FH 2 A 0 0 H 2A00H 2A00H2A00H 2, 2, 200H 2, 2, 200H 200H 2 0 0 H 200H 1 1 2A0 H 000FH 0 0 0 F H 000FH 1 STORE R2, [200H] Memory[200H]=R2 Computer Architecture (E Edwards) 8.29 CPU ALU 1A01H 3A02H 2A00H 0000 0009 0006 RAM 000 001 3FD 3FE 3FF 14 080 081 082 200 201 202083H 000FHR2 PC 0 FH STORE R2, [200H] Memory[200H]=R2 00FH 200H 1 00FH 200H 1 Computer Architecture (E Edwards) 8.30 Think About Fetch-Execute Cycle Assembly Languages Program Representation: Instructions, Instruction Fields, Instruction Formats CPU Components: Registers, ALU, Control Unit Registers: General Purpose Registers, Program Counter (PC), Instruction Register (IR), ALU Registers Buses: Internal, Address, Data, Control