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MIPS Load & Stores Today’s lecture MIPS Load & Stores  Data Memory  Load and Store Instructions  Encoding  How are they implemented? State – the central concept of computing Instructions and Control Logic What happens when the register file can be only so big? 5 5 5 32 32 We need more space! Registers Fast Synchronous Small (32x32 bits) Expensive Main Memory Slow Not always synchronous Large (232B) Cheap-ish Harvard Architecture stores programs and data in separate memories Instruction memory:  Contains instructions to execute  Treat as read-only Data memory:  Contains the data of the program  Can be read/written Data Memory is byte-addressable with 232 bytes word_we byte_we Operation 0 0 Read (Load) DATA_OUT = M[ADDR] 0 1 Write (Store) byte in ADDR M[ADDR] = DATA_IN[7:0] 1 0 Write (Store) word in ADDR M[ADDR]† = DATA_IN[31:0] 32 32 32 word_we DATA_IN ADDR DATA_OUT byte_we clk reset reset †(ADDR[1:0] must be word aligned) We can load or store bytes or words Load Store Word lw R[rt] = M[ADDR][31:0] sw M[ADDR] = R[rs][31:0] Byte lb R[rt] = SEXT(M[ADDR][7:0]) lbu R[rt] = ZEXT(M[ADDR][7:0]) sb M[ADDR] = R[rs][7:0] Indexed addressing derives ADDR from a base “pointer” register and a constant Register File … $4 $5 $6 Base Pointer $7 $8 $9 … … … 0x20030400 0x20030401 0x20030402 0x20030403 0x20030404 0x20030405 … … Data Memory PosOffset Ne g Of fs et lw rt, rs, imm sw rt, rs, imm Destination Base Offset Load word (lw) is Little Endian lw $12, 0($3) Register File … … $3 0x10010000 … … $12 … … … 0x10010000 0x00 0x10010001 0x11 0x10010002 0x22 0x10010003 0x33 … … Data Memory sw $12, 0($3) Register File … … $3 0x10010000 … … $12 0xAABBCCDD … … … 0x10010000 0x10010001 0x10010002 0x10010003 … … Data Memory a) 0xAA b) 0xBB c) 0xCC d) 0xDD lbu $12, 1($3) Register File … … $3 0x10010000 … … $12 … … … 0x10010000 0x10010001 0x10010002 0x10010003 0x10010004 0x10010005 0x10010006 0x10010007 0X10010008 … … Data Memory a) b) c)  d) e) Where is data read from? lbu $12, 1($3) Register File … … $3 0x10010000 … … $12 … … … 0x10010000 xF1 0x10010001 xF2 0x10010002 xF3 0x10010003 xF4 … … Data Memory What data is loaded into the register? a)0x0000F200 b)0x000000F2 c)0xFFFFF200 d)0xFFFFFFF2 sb $12, 2($3) Register File … … $3 0x10010000 … … $12 xAABBCCDD … … … 0x10010000 0x10010001 0x10010002 0x10010003 … … Data Memory What data is stored into memory? a)xAA b)xBB c)xCC d)xDD int a = 10; int b = 0; void main() { b = a+7; } Convert C code into MIPS assembly int a = 10; int b = 0; void main() { b = a+7; } Convert C code into MIPS assembly .data a: .word 10 b: .word 0 .text main: la $4, a 0x10010000 0x10010001 0x10010002 0x10010003 0x10010004 0x10010005 0x10010006 0x10010007 Data Memory int a = 10; int b = 0; void main() { b = a+7; } Which code finishes converting C code into MIPS assembly? .data a: .word 10 b: .word 0 .text main: la $4, a 0x10010000 0x10010001 0x10010002 0x10010003 0x10010004 0x10010005 0x10010006 0x10010007 Data Memory lw $5, 0($4) addi $5, $5, 7 sw $5, 0($4) lw $5, 0($4) addi $5, $5, 7 sw $5, 1($4) lw $5, 0($4) addi $5, $5, 7 sw $5, 2($4) A B C lw $5, 0($4) addi $5, $5, 7 sw $5, 4($4) D $4 = 0x10010000 int a = 10; int b = 0; void main() { b = a+7; } Convert C code into MIPS assembly .data a: .word 10 b: .word 0 .text main: la $4, a lw $5, 0($4) addi $5, $5, 7 sw $5, 4($4) 0x10010000 0x10010001 0x10010002 0x10010003 0x10010004 0x10010005 0x10010006 0x10010007 Data Memory Loads and stores use the I-type format op rs rt address 6 bits 5 bits 5 bits 16 bits lw, lb, lbu base source offset sw, sb base dest offset clk reset alu_op[2:0] A[31:0] B[31:0] out[31:0] overflow negative alu_src2 32 imm16 32 32 32 3 A_addr B_addr W_addr A_data B_data W_en W_data reset 25x32 Register File A B out 0 1 s 31'b0 10 slt 16'b0 16 lui 1 0 word_we byte_we addr[31:0] data_out[31:0] data_in[31:0] word_we byte_we Data Memory reset 32 32 imm32 zero store implemented sw $5, 4($4) clk reset alu_op[2:0] A[31:0] B[31:0] out[31:0] overflow negative alu_src2 32 imm16 32 32 32 3 A_addr B_addr W_addr A_data B_data W_en W_data reset 25x32 Register File A B out 0 1 s 31'b0 10 slt 16'b0 16 lui 1 0 word_we byte_we addr[31:0] data_out[31:0] data_in[31:0] word_we byte_we Data Memory reset 32 32 imm32 zero load word implemented lw $5, 4($4) clk reset alu_op[2:0] A[31:0] B[31:0] out[31:0] overflow negative alu_src2 32 imm16 32 32 32 3 A_addr B_addr W_addr A_data B_data W_en W_data reset 25x32 Register File A B out 0 1 s 31'b0 10 slt 16'b0 16 lui 1 0 word_we byte_we addr[31:0] data_out[31:0] data_in[31:0] word_we byte_we Data Memory reset 32 32 imm32 zero load byte unsigned implemented lbu $5, 4($4) Full Machine Datapath – Lab 6 wr_enable clk reset alu_op[2:0] A[31:0] B[31:0] out[31:0]0 1 s overflow zero negative alu_src2 alu_op[2:0] write_enable alu_src2 rd_src 3 inst[31:0] inst[25:21] inst[20:16] inst[15:11] inst[20:16] rd_src rs rt rd rt 5 5 5 16 6 6 32 inst[15:0] inst[31:26] inst[5:0] imm16 32 32 32 3 32 3 ADD 4 32 32 1 30 PC[31:0] nextPC[31:0] PC[31:2] except A_addr B_addr W_addr A_data B_data W_en W_data reset 25x32 Register File MIPS instruction decoder alu_op[2:0] write_enable alu_src2 rd_src except opcode[5:0] funct[5:0] A B out 0 1 s Instruction Memory addr[29:0] data[31:0] PC Register D[31:0] Q[31:0] reset enable 3 ADD branch offset 32 ALU 0 1 2 3 PC+4[31:28] 2'b0 ALU control_type inst[25:0] 26 4 32 3232 32 32 32 control_type[1:0] 2 control_type[1:0] zero 32<<2 in[29:0] out[31:0] Sign Extender in[15:0] out[31:0] branch offset 30'b0 10 slt 16'b0 16 lui 1 0 luilui sltslt word_we byte_we out[1:0] da ta _o ut [3 1: 0] da ta _o ut [3 1: 24 ] da ta _o ut [2 3: 16 ] da ta _o ut [1 5: 8] da ta _o ut [7 :0 ] mem_read byte_load 32 1 0 addr[31:0] data_out[31:0] data_in[31:0] word_we byte_we Data Memory reset 0123 1 0 24'b0 32 32 32 32 32 byte_loadbyte_load word_weword_we byte_webyte_we mem_readmem_read