Java程序辅导

andrew yu
andrew.chris.yu@gmail.com acyu@mit.edu github.com/phonon (707) 364-7782
Education
2018 – Now Massachusetts Institute of Technology (MIT)
PhD Student, EECS
2013 – 2018 Stanford University
M.S. Electrical Engineering, GPA: 4.13
B.S. Electrical Engineering, GPA: 3.94
Minor History
2009 – 2013 Cardinal Newman High School
Valedictorian
Work/Research Experience
2018 – Now Researcher, Prof. Max Shulaker lab, MIT Electrical Engineering
3D monolithic integrated circuits, carbon nanotube electronics
2017 Xilinx, San Jose, Intern
High speed SAR ADC design in 16nm FinFET, modelling thermal noise and metastability
2014 – 2018 Researcher, Prof. Eric Pop lab, Stanford Electrical Engineering
“2D” transition-metal dichalcogenides, semiconductor-metal contact optimization
2016 – 2018 Head Teaching Assistant, Stanford, ENGR40: Introductory Electronics
Course development, gave lectures, managed lab (supplies, project, ...)
2011 Volunteer, Seeds of Learning, El Salvador
Selected Awards/Recognitions/Honors
2018 National Science Foundation (NSF) Graduate Research Fellowship
2017 Phi Beta Kappa
2017 Tau Beta Pi
2016 Stanford EE315 SAR ADC Design Contest Winner
“Most Courageous.” 11-bit, 3.1 mW, 180-MS/s Asynchronous Loop-Unrolled SAR.
2016 Stanford EE214B Transimpedance Amplifier Design Contest Winner
“Most Intriguing Circuit.” 5-stage inverter TIA with local and global feedback.
Research Publications
8. C. Lau, G. Hills, M. Bishop, T. Srimani, R. Ho, P. Kanhaiya, A.C. Yu, A. Amer, M. Chao, M.M.
Shulaker, “Manufacturing Methodology for Carbon Nanotube Electronics,” VLSI, 134-135, 2020.
7. T. Srimani, G. Hills, M. Bishop, C. Lau, P. Kanhaiya, R. Ho, A. Amer, M. Chao, A.C. Yu, A. Wright,
A. Ratkovich, D. Aguilar, A. Bramer, C. Cecman, A. Chov, G. Clark, G. Michaelson, M. Johnson, K.
Kelley, P. Manos, K. Mi, U. Suriono, S. Vuntangboon, H. Xue, J. Humes, S. Soares, B. Jones, S. Burack,
A. Chandrakasan, B. Ferguson, M. Nelson, M.M. Shulaker, “Heterogeneous Integration of BEOL Logic
and Memory in a Commercial Foundry: Multi-Tier Complementary Carbon Nanotube Logic and
Resistive RAM at a 130 nm node,” VLSI, 1-2, 2020.
6. A.C. Yu, D. Bankman, K. Zheng, B. Murmann, “Understanding Metastability in SAR ADCs: Part II:
Asynchronous,” IEEE Solid-State Circuits Magazine 11 (3), 2019.
5. D. Bankman, A.C. Yu, K. Zheng, B. Murmann, “Understanding Metastability in SAR ADCs: Part I:
Synchronous,” IEEE Solid-State Circuits Magazine 11 (2), 2019.
4. C.J. McClellan, A.C. Yu, C.H. Wang, H.-S.P. Wong, E. Pop, “Vertical Sidewall MoS2 Growth and
Transistors.” Device Research Conference, 65-66, 2019.
3. M.J. Mleczko, A.C. Yu, C.M. Smyth, Y.C. Shin, V. Chen, Y.-C. Tsai, Y. Nishi, R.M. Wallace, E. Pop,
“Contact Engineering High Performance n-Type MoTe2 Transistors.” Nano Letters, 2019.
2. C.-H. Wang, J.A. Currivan-Incorvia, C. McClellan, A.C. Yu, M.J. Mleczko, E. Pop, H.-S.P. Wong,
“Unipolar n-type Black Phosphorus Transistor with Low Work Function Contacts,” Nano Letters 18 (5),
2822-2827, 2017.
1. A.C. Yu, “Contact Engineering n-Type Molybdenum Ditelluride Transistors,” B.S. Thesis, Dept. Elec.
Eng., Stanford Univ., Stanford, CA, May 2017. http://purl.stanford.edu/nm404yh0848
Conference Proceedings
2. C.-H. Wang, J.A. Currivan-Incorvia, C. McClellan, A.C. Yu, M.J. Mleczko, E. Pop, H.-S.P. Wong,
“N-type Black Phosphorus Transistor with Low Work Function Contacts,” SRC TECHCON, Sep 2017,
Austin, TX.
1. M.J. Mleckzo, A.C. Yu, Y.C. Shin, C. Smyth, R.M. Wallace, Y. Nishi, E. Pop, “De-Pinning Metal
Contacts to MoTe2 Using Monolayer h-BN,” Contributed Presentation, MRS Spring Meeting, Apr 2017,
Phoenix AZ.
Personal Projects
2020 – 2021 Minecraft Server Plugin Development
World management, vehicles, guns, ∼30k lines code (kotlin, rust, java)
2013 – 2015 StarCraft II Sandbox/Roleplaying Engine Mod
Roleplaying/storytelling sandbox engine, 500+ users

Relevent Skills
ˆ Software:
– 10000s lines code: Kotlin, JavaScript
– 1000s lines code: Rust, C, Python, MATLAB
– Other: Java, Verilog, HTML/CSS
ˆ Circuit design/simulation/layout: Cadence Virtuoso, HSPICE
ˆ Semiconductor Fabrication: CMOS processing, transistor characterization, cleanroom (6 years)
ˆ Photoshop (7 years) , Drawing/Painting (13 years)