Java程序辅导
C C++ Java Python Processing编程在线培训 程序编写 软件开发 视频讲解
C C++ Java Python Processing编程在线培训 程序编写 软件开发 视频讲解
© 2002 Edward F. Gehringer ECE 463/521 Lecture Notes, Fall 2002 1 Figures from CAQA used with permission of Morgan Kaufmann Publishers. © 2003 Elsevier Science (USA) The MIPS Instruction-Set Architecture [H&P §2.12] The MIPS instruction set illustrates four underlying principles of hardware design: 1. Simplicity favors regularity. 2. Smaller is faster. 3. Good design demands compromise. 4. Make the common case fast. The MIPS instruction-set architecture has characteristics based on conclusions from previous lectures. • It is a load-store architecture that uses general-purpose registers. • It has only two addressing modes, displacement and immediate, but can synthesize other important modes from them. • It supports 8-, 16-, 32-, and 64-bit integers, and 32- and 64- bit IEEE 754 floating-point numbers. • It has an orthogonal set of instructions to manipulate these data types. • It has separate comparison and branching instructions. (This is an example of making the common case fast.) MIPS has thirty-two 64-bit general-purpose registers, named R0, R1, … , R31. R0 always contains 0 (loading it with another value has no effect). It has 32 floating-point registers, which can hold either single- precision (32-bit) or double-precision (64-bit) values. This is an example of smaller is faster—using a single register set would make register-address fields larger and make accesses take longer. Lecture 13 Advanced Microprocessor Design 2 Addressing modes Displacement and immediate modes both have 16-bit fields. How can we synthesize other important addressing modes? › Register indirect: › Direct: › Scaled: › Memory indirect: Like the PowerPC, MIPS can select either Big Endian or Little Endian byte ordering. Memory is byte addressable with a 64-bit address. MIPS instruction formats Simplicity favors regularity … so all MIPS arithmetic instructions have exactly three operands. For example, DADD R3, R1, R2 Regs[R3] ← Regs[R1] + Regs[R2] DSUB R3, R1, R2 Regs[R3] ← Regs[R1] – Regs[R2] Good design demands compromise … so instructions are fixed length (32 bits). This requires different instruction formats. This table gives a summary of the three formats. Format 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits Comments R op rs rt rd shamt funct Arithmetic I op rs rt address/immediate Transfer, branch, immediate J op target address Jump © 2002 Edward F. Gehringer ECE 463/521 Lecture Notes, Fall 2002 3 Figures from CAQA used with permission of Morgan Kaufmann Publishers. © 2003 Elsevier Science (USA) Let’s take a look at each of these formats in more detail. An R-type instruction has this format. 6 5 5 5 5 6 Opcode rs rt rd shamt funct ALU op Operand 1 Operand 2 Result Shift amt. add, sub, etc. This format is used for both arithmetic and boolean operations. In general, the shamt field is 0 for arithmetic operations, and the rs field is 0 for logical operations. An I-type instruction has this format. 6 5 5 16 Opcode rs rt Immediate Load/Store Source register Destination register Immediate [rt ← rs op immediate] Conditional branch Comparand 1 Comparand 2 PC-relative offset [if rs rel rt then branch] A J-type instruction has this format. 6 26 Opcode Offset Jump [& link] Target address4..29 Jump register Register to jump to JR function code MIPS instructions Here are a few MIPS instructions. The text has another list, and a comprehensive list (for MIPS IV) can be found at techpubs.sgi.com/library/manuals/2000/ 007-2597-001/pdf/007-2597- 001.pdf Lecture 13 Advanced Microprocessor Design 4 Arithmetic instructions Instruction Example Meaning Comments Add ADD R1,R2,R3 R1←R2+R3 Subtract SUB R1,R2,R3 R1←R2–R3 Add immediate ADDI R1,R2,10 R1←R2+10 Adds a constant Add unsigned ADDU R1,R2,R3 R1←R2+R3 No trap on o’flo. Add immed uns’d ADDIU R1,R2,10 R1←R2+10 Logical instructions Instruction Example Meaning Comments And AND R1,R2,R3 R1←R2&R3 Or OR R1,R2,R3 R1←R2|R3 And immediate ANDI R1,R2,10 R1←R2&10 and with a constant Shift left logical SLL R1,R2,10 R1←R2<<10 Shift left by constant Shift right logical SRL R1,R2,10 R1←R2>>10 Shift right by constant Load/store Instruction Example Meaning Comments Load word LW R1,10(R2) R1←Mem [R2+10] Memory to register Store word SW R1,10(R2) Mem[R2+10] ←R1 Register to memory Load upper immed. LUI R1,10 R1←10×2 16 Load constant into upper 16 bits of word Conditional branch Instruction Example Meaning Branch on equal BEQ R1,R2,10 if (R1==R2) goto PC+4+10 Branch on not equal BNE R1,R2,10 if (R1!=R2) goto PC+4+10 Set on less than SLT R1,R2,R3 if (R2