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1Register File Design 
and
Memory Design
Presentation E
CSE 675.02: Introduction to Computer Architecture
Slides Gojko Babić
g. babic 2
Register File
• MIPS register file includes 32 32-bit general purpose 
registers
• This register file makes possible to simultaneously read from 
two registers and write into one register as it is appropriate for 
MIPS processor.
R e a d r e g is te r
n u m b e r 1 R e a d
d a ta 1
R e a d
d a ta 2
R e a d r e g is te r
n u m b e r 2
R e g is te r f i le
W r i te
r e g is te r
W r i te
d a ta W r it e
5
5
5
32
32
32
Figure B.8.7
Studying assignment: B.9
2g. babic Presentation E 3
• A register file functions as follows:
– any value provided on 5-line Read register number 1 
port results in the content of the corresponding register 
being provided on the 32-line Read data 1 port
– any value provided on 5-line Read register number 2 
port results in the content of the corresponding register 
being provided on the 32-line Read data 2 port
– on the falling edge of write line, values that appear on 
32-bit Write data port are written into the register with 
the number specified on the 5-line Write register port.
Note that requirements for set-up time (and hold time) 
also apply here.
Register File Functioning
g. babic Presentation E 4
Register File Design: Read Part
This is the RF design at the level of registers and multiplexers.
Read register
number 1 Read
data 1
Read
data 2
Read register
number 2
Register file
Write
register
Write
data Write
5
5
32
32
M
u
x
Register 0
Register 1
Register n– 1
Register n
M
u
x
Read data1
Read data2
Read register
number 1
Read register
number 2
n=31
Figure B.8.8
3g. babic Presentation E 5
Register File Design: Write Part
n-to-1
decoder
Register 0
Register 1
Register n –  1
C
C
D
D
Register n
C
C
D
D
Register number
Write
Register data
0
1
n –  1
n
n=31
32
5
Read register
number 1 Read
data 1
Read
data 2
Read register
number 2
Register file
Write
register
Write
data Write
5
32
Figure B.8.9
g. babic Presentation E 6
• Main memory is built in one of two technologies:
– SRAM - Static Random Access Memory
– DRAM - Dynamic Random Access Memory
• Both memory technologies are volatile
• A memory is normally built using a number of memory chips. 
• Memory chips have specific configurations given as a product 
of two numbers, e.g.
– 128M*1 – 128M addressable locations with 1 bit in each 
location, i.e. width of read/write operations is 1 bit
– 16M*8 – 16M addressable locations with 8 bits in each  
location, i.e. width of read/write operations is 8 bits
• Notice that two chips above accommodate identical number 
of bits (128M bits).
Introduction to Memory Design
4g. babic Presentation E 7
• In SRAM technology, three-state D-latch is a basic building 
block, i.e. basic memory cell. Internally, D-latch can have a 
state corresponding to 0 or 1.
• In DRAM technology, a basic memory cell is build around 
one capacitor coupled with one transistor. The value in the 
cell is stored as a charge. A charge can not be stored 
indefinitely and DRAM chips must be periodically refreshed. 
Since charge can be kept for several msec, 1-2% of time is 
used for refreshing.
SRAM and DRAM: 1 Bit Memory Cell
g. babic Presentation E 8
DRAM & SRAM Characteristics
Access time & cycle time are two measures of memory latency:
• access time – the time between a read is requested and when
the desired content arrives,
• cycle time – the minimum time between two memory requests.
• Since 1975, the main memory has been implemented using 
semiconductor DRAM’s.
DRAM chip capacity had been growing at rate of about 4 times
every three years, while lately growth slowed down to 2 times
every two years. 
Current DRAM chip capacity has reached 4GB on a single 
memory module with an access time in the range 40-60 nsec
and a cycle time of about 80 nsec.
• SRAM – technology is normally used for caches.
5g. babic Presentation E 9
DRAM & SRAM Characteristics (Cont.)
• Thus SRAM designs are concerned with speed, while in DRAM
designs the emphasis is on cost per bit and capacity.
• But, SRAM chip capacity (as well as density) is roughly 4 to 8   
times less than that of DRAM 
• Also, SRAM is more expensive, e.g. 1GB in 2004 $4,000 –
$10,000 for SRAM and $100 – $200 for DRAM.
• In comparable technologies, SRAM cycle time is about 8 to 16 
times faster than DRAM, e.g. currently 0.5-5 nsec.
• In addition, SRAM chips have higher power consumption and 
power dissipation than DRAM chips.
• For DRAM technology cycle time is longer than access time.
– One of the reasons: Since a read is destructive in DRAM 
technology, any read has to be followed  by internal write
with values just read.
• For SRAM technology access time and cycle time are identical.
g. babic Presentation E 10
Memory Chip Functioning
• Functioning of memory chip:
– CS (Chip select) has to be set for either reading or writing
– R (Read enable)=0 & W (Write enable)=0  chip is not being accessed
– R=0 and W=1  write values at Din lines into the chip address at 
Address lines
– R=1 and W=0  read into Dout lines values from the chip address at 
Address lines 
– R=1 and W=1  not allowed
Example: 32K×8 chip
• read and write
operations are 8 bits
wide
• there are 32K 
addressable locations
Two designs of memory chip: – Basic structure design
– Typical organization design
R A M
3 2 K  8
8
1 5
8
D o u t [ 7 – 0 ]
A d d r e s s
C h i p s e l e c t
D i n [ 7 – 0 ]
Read enable
Write enable
6g. babic Presentation E 11
Din[0]D in[1 ]
D
latch Q
D
C
Enable
D
latch Q
D
C
Ena ble
D
latch Q
D
C
Enable
D
latch Q
D
C
Ena ble
D
latch Q
D
C
Enable
D
la tch Q
D
C
Ena ble
D
latch Q
D
C
Enable
D
latch Q
D
C
Ena ble
2-to-4
decod er
e enab le
Address
D ou t[1 ] D out[0]
0
1
2
3
Basic Structure Design of 4×2 SRAM Chip
SR AM
4  2
2
2
2
D ou t[1– 0]
A ddre ss
C h ip se lec t
O u tput enab le
W rite ena ble
D in [1– 0]W rit
Read Enable
Chip Select
Figure B.9.3
g. babic Presentation E 12
• The basic structure design of SRAM chip uses some ideas 
from the register file design e.g. the write parts in two 
designs are identical. The main differences are in read part 
design. In the memory chip with the usage of three-state D-
latches a multiplexer is eliminated. E.g. for 32K*8 SRAM 
chip, a multiplexer with 32K inputs each input having 8 lines 
would be needed.
• But for the basic structure design of SRAM chip, we still 
need a very large decoder. E.g. for 32K*8 SRAM chip, a 
decoder with 15 input lines (that is not so bad) and 32K 
output lines (that is bad) is required. 
• The typical organization design uses two level decoding that 
eliminates need for that very large decoder. 
Basic Structure Design
7g. babic 13
Din[0]D in[1 ]
D
latch Q
D
C
Enable
D
latch Q
D
C
Enable
D
latch Q
D
C
Enable
D
latch Q
D
C
Enable
D
latch Q
D
C
Enable
D
latch Q
D
C
Enable
D
latch Q
D
C
Enable
D
latch Q
D
C
Enable
2-to-4
decoder
e enab le
Address
D ou t[1 ] D out[0]
0
1
2
3
4×2 Array of D- Latches
W rit
Read Enable
Chip Select
E
C
E
C
E
C
E
C
The next example will be using 512×64 array of D-latches.
g. babic Presentation E 14
5 1 2  6 4
S R A M
M u x
D o u t7
5 1 2  6 4
S R A M
M u x
D o u t6
5 1 2  6 4
S R A M
M u x
D o u t5
5 1 2  6 4
S R A M
M u x
D o u t4
5 1 2  6 4
S R A M
M u x
D o u t3
5 1 2  6 4
S R A M
M u x
D o u t2
5 1 2  6 4
S R A M
M u x
D o u t1
5 1 2  6 4
S R A M
M u x
D o u t0
9 - to -5 1 2
de co d e r
A d d r e s s
[1 4– 6 ]
6 4
5 1 2
A d d r e s s
[5 – 0 ]
• Example:Design (read part only) a typical organization (i.e. two level 
decoding design) of 32K×8 SRAM chip that uses 512*64 arrays of D-
latches.
• Note: Arrays used have to have a bit capacity equal to a number of 
addressable locations in the chip, e.g. in this example that condition 
is satisfied since 512*64 = 32K. A number of arrays used should be 
equal to the number of bits in each memory location. 
Typical Organization Design
Also see Figure B.9.4 with another example of typical organization.
DRAM memory chip would have similar design.
8g. babic Presentation E 15
• A memory has identical inputs and outputs as memory chips, 
except that CS does not exist. But the specification of a 
memory should include:
a. memory capacity (usually in bytes),
b. memory addressability, i.e. smallest unit that has its 
address,
d. width of read/write operations, i.e. a number of bits that can 
be read or written from/to memory.
• Operations on memory: reading from memory and writing into 
memory;
– RE=0 and WE=0  memory is not being accessed
– RE=0 and WE=1  writing into memory
– RE=1 and WE=0  reading from memory
– RE=1 and WE=1  not allowed
Main Memory Specification