Java程序辅导
C C++ Java Python Processing编程在线培训 程序编写 软件开发 视频讲解
C C++ Java Python Processing编程在线培训 程序编写 软件开发 视频讲解
Nahid Farhady Ghalaty 306 D, Department of Computer Science, Texas Tech University, Lubbock, TX, USA nahid.farhady@ttu.edu +() - rijndael.ece.vt.edu/farhady Research Interests Embedded System Design: Security, Reliability and Performance Perspectives Cryptographic Engineering: Design and Implementation of Novel Cryptosystems Computer Architecture Hardware Software Co-design Work Experience Assistant Professor, Department of Computer Science, Texas Tech University, TX, USA Education – Ph.D. in Computer Engineering, Virginia Polytechnic Institute and State University, VA, USA esis:\Fault Attacks on Cryptosystems: Novel Threat Models, Countermeasures and Evaluation Metrics".Advisor: Dr. Patrick Schaumont - M.Sc. in Computer Architecture, Sharif University of Technology, Tehran, Iran esis: \A Post-Processor for Control Flow Checking of Jump and Branch Instructions". Advisor: Dr. Seyed Ghassem Miremadi - B.Sc. in Software Engineering, Shahid Chamran University of Ahvaz, Ahvaz, Iran esis: \An ACO-GA Based Method to Solve Symmetric Traveling Salesman Problem". Advisor: Dr. Masoud Mazloom Honors & Awards Winner of scholarship to attend the Academic Leadership forWomen in Engineering, Philadelphia, PA Winner of Outstanding Graduate Student Award at Virginia Tech CESCA day Winner of Best Paper in Session Award at SRC Techcon, Austin, TX Winner of Best Poster Award at Virginia Tech CESCA day among 40+ participants Selected as the Member of Alpha Epsilon Lambda Honor Society at Virginia Tech Winner of Best Presentation Award at Virginia Tech CESCA day among 40+ participants Winner of A. Richard Newton Young Student fellowship award to attend Design Automation Conference (DAC), San Fransisco, CA Winner of scholarship to attend the CRA-Women Grad Cohort Workshop, Santa Monica, CA Selected as theVice President for Council of International Student Organizations Selected as the President of Iranian Society at Virginia Tech Winner of scholarship to attend the GREPSEC workshop, San Fransisco, CA Winner of Best Paper Award at CADS, Shiraz, Iran Awarded the Virginia Tech Graduate Research Assistantship with Full Tuition Exemption and Monthly Stipend Ranked 3rd in the FPGA Design Contest at Sharif University of Technology Ranked 3rd in the Computer Engineering students (50+) of Shahid Chamran University of Ahvaz Honors & Awards (Cont.) Ranked 71st in National Entrance Exam for Graduate Students in Computer Architecture among 300000 participants, Iran Selected as an Exceptional Talent among the B.Sc. Computer Engineering Students among 50+ participants, Ahvaz, Iran Publications Book Chapter S N. F. Ghalaty, B. Yuce, P. Schaumont, A Systematic Approach to Fault Attack Resistant Design, S. Bhunia, S. Ray and S. Sur-Kolay [Editors], Fundamentals of IP and SoC Security- Design Veri cation and Debug, Springer International Publishing, New York, USA. Journal Articles ESL- N. F. Ghalaty, B. Yuce, P. Schaumont, Analyzing the Eciency of Biased-Fault Based Attacks, IEEE Embedded Systems Letters , vol.PP, no.99, pp.1-1. IEEE TC- H. Farbeh, N. Mirzadeh, N. F. Ghalaty, S.G. Miremadi, M. Fazeli, H. Asadi, A Highly Reliable Cache-Assisted ScratchPad Memory, IEEE Transactions on Computers, Accepted. Peer Reviewed Conference and Workshop Proceedings SRC- B. Yuce, N. F. Ghalaty, C. Deshpande, C. Patrick, L. Nazhandali, P. Schaumont, FAME: Fault-attack Aware Microprocessor Extensions for Hardware Fault Detection and Soft- ware Fault Response, Semiconductor Research Corporation Techcon, Austin, TX, 2016. SAC- C. Patrick, B. Yuce, N. F. Ghalaty, P. Schaumont, Lightweight Fault Attack Resistance in Software Using Intra-Instruction Redundancy, Selected Areas in Cryptography (SAC), St. John's, Canada, 2016. FDTC- B. Yuce, N. F. Ghalaty, H. Santapuri, C. Deshpande, C. Patrick, P. Schaumont, Software Fault Resistance is Futile: E ective Single-glitch Attacksn, Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC), Santa Barbara, CA, 2016. ISVLSI- C. Deshpande, B. Yuce, N. F. Ghalaty, D. Ganta, P. Schaumont, L. Nazhandali, A Con- gurable and Lightweight Timing Monitor for Fault Attack Detection, IEEE Computer Society Annual Symposium on VLSI, Pittsburgh, PA, 2016. HASP- B. Yuce, N. F. Ghalaty, C. Depande, C. Patrick, L. Nazhandali, P. Schaumont, FAME: Fault-attack Aware Microprocessor Extensions for Hardware Fault Detection and Soft- ware Fault Response, Proceedings of the FifthWorkshop onHardware and Architectural Support for Security and Privacy, 2016. SRC- N. F. Ghalaty, B. Yuce, L. Nazhandali, P. Schaumont, FAME: Fault-Attack Awareness using Microprocessor Enhancements, Winner of Best Paper in Session Award, Semiconductor Research Corporation Techcon, Austin, TX, 2015. FDTC- B. Yuce, N. F. Ghalaty, P. Schaumont, Improving Fault Attacks on Embedded Software using RISC Pipeline Characterization,Workshop on Fault Diagnosis and Tolerance in Cryp- tography (FDTC), Saint Malo, France, 2015, pp. 97-108. COSADE- N. F. Ghalaty, B. Yuce, P. Schaumont, Di erential Fault Intensity Analysis on PRESENT and LED Block Ciphers, Constructive Side-Channel Analysis and Secure Design, 2015, Berlin, Germany, pp. 174-188. Springer International Publishing. Page 2 Nahid Farhady Ghalaty Publications (Cont.) HOST- B. Yuce, N. F. Ghalaty, P. Schaumont, TVVF: Estimating the Vulnerability of Hard- ware Cryptosystems against Timing Violation Attacks, IEEE International Symposium on Hardware Oriented Security and Trust (HOST), Washington, DC, 2015, pp. 72-77. FDTC- N. F. Ghalaty, B. Yuce, M. Taha, P. Schaumont, Di erential Fault Intensity Analysis, Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC), Busan, South Korea, 2014, pp. 49-58. DATE- N. F. Ghalaty, A. Aysu, P. Schaumont, Analyzing and Eliminating the Causes of Fault Sensitivity Analysis, Design, Automation and Test in Europe Conference and Exhibi- tion (DATE), Dresden, Germany, 2014, pp. 1-6. WESS- A. Aysu,N. F. Ghalaty, Z. Franklin, M. P. Yali, P. Schaumont,Digital Fingerprints for Low- Cost Platforms using MEMS Sensors, Proceedings of the Workshop on Embedded Systems Security, Quebec, Canada, 2013, pp. 1-6. ACM. CADS- S.N. Ahmadyn,M. Fazeli,N. F. Ghalaty, S.G.Miremadi,Value-Aware Low-Power Register File Architecture, Winner of Best Paper Award, 16th CSI International Symposium on Computer Architecture and Digital Systems (CADS), Shiraz, Fars, 2012, pp. 44-49. IOLTS- N. F. Ghalaty, M. Fazeli , H. Izadirad, S.G. Miremadi, Software-Based Control Flow Error Detection and Correction Using Branch Triplication, 2011 IEEE 17th International On-Line Testing Symposium (IOLTS), Athens, Greece, 2011, pp. 214-217. Poster Presentations CHES- FAME: Fault Attack Awareness Using Microprocessor Enhancements CESCA- DFIA: e Earth in Fault Attack Universe, Winner of Best Poster Award DAC- Fault Sensitivity Analysis, Causes and Countermeasures CESCA- New Directions in Fault Attacks: FSA & DFIA, Winner of Best Presentation Award CRA-W- Fault Attacks and Countermeasures by Delay Balancing Invited Talks S' “New Directions in Hardware Security: Novel Fault Attacks and reat Models”,Department of Computer Science, Texas Tech University, Lubbock, TX, USA S' “Security Pitfalls in Cryptography: Walls May Have EARS!”, Department of Computer Science, College of Charleston, Charleston, SC, USA S' “New Directions in Hardware Security: Novel Attacks and reat Models”, Department of Computer Engineering, Florida Polytechnic University, Lakeland, FL, USA S' “Security Pitfalls in Cryptography”, Department of Computer Engineering & Com- puter Science, California State University Long Beach, Long Beach, CA, USA S' “Advances in Fault Attacks and reat Models”,Donal Bren School of Information and Computer Science, University of California Irvine, Irvine, CA, USA Page 3 Nahid Farhady Ghalaty Invited Talks (Cont.) S' “Security Pitfalls in Cryptography: Walls May Have EARS!”, Department of Computer Science, Appalachian State University, Boone, NC, USA F' “Security for 'Internet of ings': Physical Attacks and Countermeasures”, Rackspace Cloud Developer Oces, Blacksburg, VA, USA S' “A New Chapter in Fault Attacks: Using Biased Faults as Leakage Information in Differential Fault Intensity Analysis”, Center for Embedded Systems for Critical Applications, Virginia Tech, Blacbsurg, VA, USA Teaching Experience A P Prepared and presented lectures, designed and graded assignments for 50+ stu- dents, course projects and exams Principals of Computer Security, Fall 2016, Texas Tech University. G TA Designed and graded research projects and presentations, Held workshop ses- sions of SHARPE/RELEX, Proposed several nal course projects Cryptographic Engineering, Spring 2016, by Dr. Schaumont, Virginia Tech. Fault Tolerant System Design, Fall 2011, by Dr. Miremadi, SUT. Electronic System Level Design, Spring 2011, by Dr. Goudarzi, SUT. T Presented lectures, designed and graded assignments for 50+ students, course projects and exams Digital Design, Computer Architecture, Spring 2012, Science and Culture higher Education Institute, Tehran, Iran. Data Structure and Algorithms, Electronic Circuits, Fall 2011, Pishtazan higher Education Institute, Tehran, Iran. Engineering Mathematics, Numerical Analysis, Summer 2010 & 2011, Preparation for M.Sc. University Entrance Exam, Fazel Institute, Shiraz, Iran. Digital Design, Arti cial Intelligence, Numerical Analysis, Engineer- ing Mathematics, Spring 2010, Fall 2010, Payam Noor University, Tehran, Iran. TA Head of four undergraduate TAs, Held weekly meetings to manage assignments and course projects for 60+ students Digital System Design, Fall 2011, by Dr. Goudarzi, SUT. Computer Architecture, Spring 2011, by Dr. Ejlali, SUT. TA Designed and graded weekly assignments, Proposed several nal course projects Microprocessors, Spring 2009, by Dr. Hassanzadeh, SCU. Operating Systems, Spring 2009, by Dr. Bohlool, SCU. L I Edited the laboratory manual, Implemented all the experiments on circuit boards and FPGAs for time management, debug and veri cation purposes Computer Architecture Lab, Summer & Fall 2011, by Dr. Asadi, SUT. Digital System Design Lab, Fall 2010, by Dr. Ejlali, SUT. Digital Circuits Lab, Spring & Fall 2008, by Dr. Ajabi, SCU. Page 4 Nahid Farhady Ghalaty Professional Memberships Member of Center for Secure Critical Applications [CESCA], Virginia Tech, 2012-present. Member of Secure Embedded Systems Lab [SES], Virginia Tech, 2012-present Member of Iran’s National Society of Exceptional Talents, 2005-present Member of Dependable Systems Lab [DSL], Sharif University of Technology, 2009-2012 Student Member of Computer Society of Iran, 2008-present Student Member at IEEE, 2011-present Service to Profession R, C COSADE-15, HOST-(16,15,14,13), ICCD-13, DATE-(16,15,14), CHES- (15,14), FDTC-(15,14), TRUEDEVICE-15, CADS-12 R, J TCAS, TECS, TC, ESL, TVLSI, TC, TECS Technical Skills P L C/C++, Java, Verilog, SystemC, GEZEL, Assembly (MIPS, SPARC) S D ModelSim, Synopsys Design Compiler, Altera Quartus II, Xilinx ISE R E SHARPE, RELEX P LEON2, LEON3, Sparkfun, Ardunio, Altera DE0-Nano/DE2-115, SASEBO, SAKURA-G Research/Industry Experience M'- A' Summer Research Intern, Department of Aerospace and Ocean Engineering, Virginia Tech Supervisors: Dr. William Devenport & Dr. Nathan Alexander Responsible for selecting a light weight, energy efficient and high performance FPGA plat- form to handle data acquisitions from 40 INMP621 microphones in rotor blades Implementation and verification of the data acquisition on theDE0-Nano FPGA board with a 250 MHZ tone generator using Pulse Density Modulation (PDM) techniques M'- S' Consultant, Parseh Institute, Tehran, Iran Provided full solution manual for the multiple choice books Digital Design, Computer Ar- chitecture, Data Structure and Algorithms, Electronic Circuits S'- A' Researcher, Dependable Systems Design Lab, Institute for Research in Fundamental Sciences, Tehran, Iran Supervisors: Dr. Seyed Ghassem Mireadmi, Dr. Mahdi Fazeli & Dr. Hossein Asadi Studied the Reliability Issues in Non-volatile Memory and Soft Error Rate Analysis in Ap- plication Level Mentoring two undergraduate students in research projects M'- A' Summer Intern, Part time Employee, Mobin Pardazesh Parseh, Shiraz, Iran Page 5 Nahid Farhady Ghalaty Research Projects Fault Attacks and Countermeasures on Processors Supported by TC: Small: New Directions in Side Channel Attacks and Countermeasures project, National Science Foundation (NSF) Award 1115839 ($437,558.00) Supported by SaTC: STARSS: FAME: Fault-attack Awareness usingMicroprocessor Enhancements project, Semiconductor Research Corporation (SRC) Award 1441710 ($460,000.00) Studied the limitations of traditional physical attack techniques Built the Differential Fault Intensity Analysis (DFIA) attack based on biased fault behavior con- tributed to the FAME proposal to SRC Implemented DFIA on hardware cryptographic primitives and LEON3 p Proposed techniques to evaluate and build fault attack resistant design Sensor-Based Physical Unclonable Functions (PUF) Surveyed several PUF structures to define a cost effective and reliable PUF Exploited process variation and static offset in the accelerators as a source of unique physical property Implemented the NIST test to quantify the reliability and uniqueness of the generated PUF Control Flow Checking (CFC) Method in Embedded Processors Surveyed the traditional CFC techniques to find out the limitations of previous methods Proposed a low cost and reliable CFCmethod based on triplication of branch and jump instructions Proposed a method to protect run-time indirect branch destination address Implemented the proposed method on the LEON2 p Verified the reliability of the proposed method by exhaustive fault injection into LEON2 p Reliable ScratchPad Memory (SPM) Developed the idea of SPM data duplication in cache Proposed read and write protocols in SPM and cache to enhance data reliability Implemented the basic idea on the LEON2 p for initial performance and reliability evaluation of the proposed technique Extracurricular University Service S' Search Committee Member, “Cranwell International Center (CIC) Director”, Invited by Dr. Tom Brown, Dean of Students, Division of Student Affairs, Virginia Tech S' Lab tour, “CS/ECE Spring Mentoring on Technical Opportunities on Campus”, Virginia Tech F' Research Areas in Hardware Security Tech Talk, “ENGR 1024: Engineering Re- search Seminar”, Bradley Department of Electrical and Computer Engineering, Virginia Tech Page 6 Nahid Farhady Ghalaty Leadership Experience Event Organizer, An Exhibition of Cultures, Art Architecture Department, Virginia Tech Event Organizer, Islam World Festival, e Moss Center for the Arts, Virginia Tech Leadership Certi cate, Alpha Epsilon Lambda Honor Society, Virginia Tech Vice President, Council for International Student Organizations (CISO), In corporation with Cranwell International Center (CIC) Event Organizer, “Women Rights”, Dr. Mohsen Kadivar, Philosopher at Duke University Event Organizer, “Are we Alone? e Search for Our Cosmetic Roots and Galactic Cousins”, Dr. Firouz Naderi, Director of Solar System Exploration Directories at NASA's JPL President, Iranian Society at Virginia Tech (ISVT) Web Master, Council for International Student Organizations Web Master, Iranian Society at Virginia Tech Notable Projects VT F' The Hardware/Software Co-design Challenge: Drawing the Mandelbrot Fractal on Altera DE2-115, Hardware/Software Co-design, Dr. Patrick Schaumont VT F' Phishing Attacks, Implementation of Detection Methods and Countermeasures, Network and Computer Security, Dr. Jungmin Park VT S' An Automated EDA Tool for Eliminating and Analyzing Fault Sensitivity Anal- ysis Using Genetic Algorithms, Electronic Design Automation, Dr. Michael Hsiao VT S' Random Number Generation Using Sensors on Smartphones, Handheld Com- puter Security, Dr. Patrick Schaumont SUT F' Analyzing Supplier Locality in Virtual Circuit Tree Multi Casting, Advanced Computer Architecture, Dr. Amirali Baniasadi SUT S' Hardware/Software Codesign of Data Encryption Standard (DES) and Imple- mentation on Xilinx Ml-403, Electronic System Level Design, Dr. Maziar Goudarzi SUT S' Design and Implementation of a Restaurant Self-Service Ordering on Xilinx ML-403, Advanced Embedded System Design, Dr. Alireza Ejlali SUT S' Technical Report on Designing a Fault Tolerant Code Generator, Advanced Fault Tolerant System Design, Dr. Seyed Ghassem Miremadi SUT F' Implementation of a Power-aware Functional Output Gating during Scan Test- ing on LEON2 Processor, Testability, Dr. Shahin Hesabi SUT F' Implementation of Advanced Encryption Standard (AES) on GPU Using CUDA based Simulations, Advanced Microprocessors, Dr. AmirHossein Jahangir SUT S' Design and Implementation of a Power-aware Disk Management Algorithm, Advanced Storage Systems, Dr. Hossein Asadi Page 7 Nahid Farhady Ghalaty