gem5: arch/mips/tlb.cc Source File gem5 Main Page Related Pages Modules Namespaces Classes Files File List File Members All Classes Namespaces Files Functions Variables Typedefs Enumerations Enumerator Friends Macros Groups Pages arch mips tlb.cc Go to the documentation of this file. 1 /* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer; 10 * redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution; 13 * neither the name of the copyright holders nor the names of its 14 * contributors may be used to endorse or promote products derived from 15 * this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * Authors: Nathan Binkert 30 * Steve Reinhardt 31 * Jaidev Patwardhan 32 * Zhengxing Li 33 * Deyuan Guo 34 */ 35 36 #include "arch/mips/tlb.hh" 37 38 #include 39 #include 40 41 #include "arch/mips/faults.hh" 42 #include "arch/mips/pagetable.hh" 43 #include "arch/mips/pra_constants.hh" 44 #include "arch/mips/utility.hh" 45 #include "base/inifile.hh" 46 #include "base/str.hh" 47 #include "base/trace.hh" 48 #include "cpu/thread_context.hh" 49 #include "debug/MipsPRA.hh" 50 #include "debug/TLB.hh" 51 #include "mem/page_table.hh" 52 #include "params/MipsTLB.hh" 53 #include "sim/process.hh" 54 55 using namespace std; 56 using namespace MipsISA; 57 59 // 60 // MIPS TLB 61 // 62 63 TLB::TLB(const Params *p) 64 : BaseTLB(p), size(p->size), nlu(0) 65 { 66 table = new PTE[size]; 67 memset(table, 0, sizeof(PTE[size])); 68 smallPages = 0; 69 } 70 71 TLB::~TLB() 72 { 73 if (table) 74 delete [] table; 75 } 76 77 // look up an entry in the TLB 78 MipsISA::PTE * 79 TLB::lookup(Addr vpn, uint8_t asn) const 80 { 81 // assume not found... 82 PTE *retval = NULL; 83 PageTable::const_iterator i = lookupTable.find(vpn); 84 if (i != lookupTable.end()) { 85 while (i->first == vpn) { 86 int index = i->second; 87 PTE *pte = &table[index]; 88 89 /* 1KB TLB Lookup code - from MIPS ARM Volume III - Rev. 2.50 */ 90 Addr Mask = pte->Mask; 91 Addr InvMask = ~Mask; 92 Addr VPN = pte->VPN; 93 if (((vpn & InvMask) == (VPN & InvMask)) && 94 (pte->G || (asn == pte->asid))) { 95 // We have a VPN + ASID Match 96 retval = pte; 97 break; 98 } 99 ++i; 100 } 101 } 102 103 DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn, 104 retval ? "hit" : "miss", retval ? retval->PFN1 : 0); 105 return retval; 106 } 107 108 MipsISA::PTE* 109 TLB::getEntry(unsigned Index) const 110 { 111 // Make sure that Index is valid 112 assert(Indexfirst == vpn) { 124 int index = i->second; 125 PTE *pte = &table[index]; 126 127 /* 1KB TLB Lookup code - from MIPS ARM Volume III - Rev. 2.50 */ 128 Addr Mask = pte->Mask; 129 Addr InvMask = ~Mask; 130 Addr VPN = pte->VPN; 131 if (((vpn & InvMask) == (VPN & InvMask)) && 132 (pte->G || (asn == pte->asid))) { 133 // We have a VPN + ASID Match 134 Ind = index; 135 break; 136 } 137 ++i; 138 } 139 } 140 DPRINTF(MipsPRA,"VPN: %x, asid: %d, Result of TLBP: %d\n",vpn,asn,Ind); 141 return Ind; 142 } 143 144 inline Fault 145 TLB::checkCacheability(RequestPtr &req) 146 { 147 Addr VAddrUncacheable = 0xA0000000; 148 // In MIPS, cacheability is controlled by certain bits of the virtual 149 // address or by the TLB entry 150 if ((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) { 151 // mark request as uncacheable 152 req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER); 153 } 154 return NoFault; 155 } 156 157 void 158 TLB::insertAt(PTE &pte, unsigned Index, int _smallPages) 159 { 160 smallPages = _smallPages; 161 if (Index > size) { 162 warn("Attempted to write at index (%d) beyond TLB size (%d)", 163 Index, size); 164 } else { 165 // Update TLB 166 DPRINTF(TLB, "TLB[%d]: %x %x %x %x\n", 167 Index, pte.Mask << 11, 168 ((pte.VPN << 11) | pte.asid), 169 ((pte.PFN0 << 6) | (pte.C0 << 3) | 170 (pte.D0 << 2) | (pte.V0 <<1) | pte.G), 171 ((pte.PFN1 <<6) | (pte.C1 << 3) | 172 (pte.D1 << 2) | (pte.V1 <<1) | pte.G)); 173 if (table[Index].V0 || table[Index].V1) { 174 // Previous entry is valid 175 PageTable::iterator i = lookupTable.find(table[Index].VPN); 176 lookupTable.erase(i); 177 } 178 table[Index]=pte; 179 // Update fast lookup table 180 lookupTable.insert(make_pair(table[Index].VPN, Index)); 181 } 182 } 183 184 // insert a new TLB entry 185 void 186 TLB::insert(Addr addr, PTE &pte) 187 { 188 fatal("TLB Insert not yet implemented\n"); 189 } 190 191 void 192 TLB::flushAll() 193 { 194 DPRINTF(TLB, "flushAll\n"); 195 memset(table, 0, sizeof(PTE[size])); 196 lookupTable.clear(); 197 nlu = 0; 198 } 199 200 void 201 TLB::serialize(CheckpointOut &cp) const 202 { 203 SERIALIZE_SCALAR(size); 204 SERIALIZE_SCALAR(nlu); 205 206 for (int i = 0; i < size; i++) { 207 ScopedCheckpointSection sec(cp, csprintf("PTE%d", i)); 208 table[i].serialize(cp); 209 } 210 } 211 212 void 213 TLB::unserialize(CheckpointIn &cp) 214 { 215 UNSERIALIZE_SCALAR(size); 216 UNSERIALIZE_SCALAR(nlu); 217 218 for (int i = 0; i < size; i++) { 219 ScopedCheckpointSection sec(cp, csprintf("PTE%d", i)); 220 table[i].unserialize(cp); 221 if (table[i].V0 || table[i].V1) { 222 lookupTable.insert(make_pair(table[i].VPN, i)); 223 } 224 } 225 } 226 227 void 228 TLB::regStats() 229 { 230 BaseTLB::regStats(); 231 232 read_hits 233 .name(name() + ".read_hits") 234 .desc("DTB read hits") 235 ; 236 237 read_misses 238 .name(name() + ".read_misses") 239 .desc("DTB read misses") 240 ; 241 242 243 read_accesses 244 .name(name() + ".read_accesses") 245 .desc("DTB read accesses") 246 ; 247 248 write_hits 249 .name(name() + ".write_hits") 250 .desc("DTB write hits") 251 ; 252 253 write_misses 254 .name(name() + ".write_misses") 255 .desc("DTB write misses") 256 ; 257 258 259 write_accesses 260 .name(name() + ".write_accesses") 261 .desc("DTB write accesses") 262 ; 263 264 hits 265 .name(name() + ".hits") 266 .desc("DTB hits") 267 ; 268 269 misses 270 .name(name() + ".misses") 271 .desc("DTB misses") 272 ; 273 274 accesses 275 .name(name() + ".accesses") 276 .desc("DTB accesses") 277 ; 278 279 hits = read_hits + write_hits; 280 misses = read_misses + write_misses; 281 accesses = read_accesses + write_accesses; 282 } 283 284 Fault 285 TLB::translateInst(RequestPtr req, ThreadContext *tc) 286 { 287 if (FullSystem) 288 panic("translateInst not implemented in MIPS.\n"); 289 290 Process * p = tc->getProcessPtr(); 291 292 Fault fault = p->pTable->translate(req); 293 if (fault != NoFault) 294 return fault; 295 296 return NoFault; 297 } 298 299 Fault 300 TLB::translateData(RequestPtr req, ThreadContext *tc, bool write) 301 { 302 if (FullSystem) 303 panic("translateData not implemented in MIPS.\n"); 304 305 Process * p = tc->getProcessPtr(); 306 307 Fault fault = p->pTable->translate(req); 308 if (fault != NoFault) 309 return fault; 310 311 return NoFault; 312 } 313 314 Fault 315 TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 316 { 317 if (mode == Execute) 318 return translateInst(req, tc); 319 else 320 return translateData(req, tc, mode == Write); 321 } 322 323 void 324 TLB::translateTiming(RequestPtr req, ThreadContext *tc, 325 Translation *translation, Mode mode) 326 { 327 assert(translation); 328 translation->finish(translateAtomic(req, tc, mode), req, tc, mode); 329 } 330 331 Fault 332 TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode) 333 { 334 panic("Not implemented\n"); 335 return NoFault; 336 } 337 338 Fault 339 TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const 340 { 341 return NoFault; 342 } 343 344 345 MipsISA::PTE & 346 TLB::index(bool advance) 347 { 348 PTE *pte = &table[nlu]; 349 350 if (advance) 351 nextnlu(); 352 353 return *pte; 354 } 355 356 MipsISA::TLB * 357 MipsTLBParams::create() 358 { 359 return new TLB(this); 360 } tlb.hh utility.hh str.hh DPRINTF #define DPRINTF(x,...) Definition: trace.hh:212 MipsISA::PTE::PFN1 Addr PFN1 Definition: pagetable.hh:63 MipsISA::TLB::index MipsISA::PTE & index(bool advance=true) Definition: tlb.cc:346 MipsISA::PTE::PFN0 Addr PFN0 Definition: pagetable.hh:57 NoFault decltype(nullptr) constexpr NoFault Definition: types.hh:189 MipsISA::TLB::serialize void serialize(CheckpointOut &cp) const override Serialize an object. Definition: tlb.cc:201 MipsISA::TLB::table MipsISA::PTE * table Definition: tlb.hh:63 MipsISA::PTE::G bool G Definition: pagetable.hh:54 MipsISA::TLB::read_hits Stats::Scalar read_hits Definition: tlb.hh:70 panic #define panic(...) Definition: misc.hh:153 MipsISA::TLB::lookup MipsISA::PTE * lookup(Addr vpn, uint8_t asn) const Definition: tlb.cc:79 BaseTLB::Write Definition: tlb.hh:61 MipsISA::PTE Definition: pagetable.hh:48 MipsISA::TLB::size int size Definition: tlb.hh:64 MipsISA::TLB::flushAll void flushAll() override Remove all entries from the TLB. Definition: tlb.cc:192 addr ip6_addr_t addr Definition: inet.hh:335 MipsISA::TLB::getEntry MipsISA::PTE * getEntry(unsigned) const Definition: tlb.cc:109 FullSystem bool FullSystem The FullSystem variable can be used to determine the current mode of simulation. Definition: root.cc:146 ThreadContext::getProcessPtr virtual Process * getProcessPtr()=0 thread_context.hh MipsISA::PTE::VPN Addr VPN Definition: pagetable.hh:51 MipsISA::TLB::regStats void regStats() override Register statistics for this object. Definition: tlb.cc:228 MipsISA::TLB::hits Stats::Formula hits Definition: tlb.hh:78 SimObject::regStats virtual void regStats() Register statistics for this object. Definition: sim_object.cc:105 ThreadContext ThreadContext is the external interface to all thread state for anything outside of the CPU... Definition: thread_context.hh:93 Request Definition: request.hh:87 trace.hh MipsISA::PTE::V1 bool V1 Definition: pagetable.hh:65 warn #define warn(...) Definition: misc.hh:219 BaseTLB Definition: tlb.hh:53 UNSERIALIZE_SCALAR #define UNSERIALIZE_SCALAR(scalar) Definition: serialize.hh:145 process.hh MipsISA::TLB::probeEntry int probeEntry(Addr vpn, uint8_t) const Definition: tlb.cc:117 MipsISA::PTE::D1 bool D1 Definition: pagetable.hh:64 MipsISA::TLB::translateAtomic Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) Definition: tlb.cc:315 pagetable.hh csprintf std::string csprintf(const char *format, const Args &...args) Definition: cprintf.hh:161 MipsISA::PTE::V0 bool V0 Definition: pagetable.hh:59 MipsISA::TLB::write_misses Stats::Scalar write_misses Definition: tlb.hh:75 PageTableBase::translate bool translate(Addr vaddr, Addr &paddr) Translate function. Definition: page_table.cc:173 MipsISA::TLB::write_hits Stats::Scalar write_hits Definition: tlb.hh:74 MipsISA::TLB::nlu int nlu Definition: tlb.hh:65 Request::UNCACHEABLE The request is to an uncacheable address. Definition: request.hh:114 MipsISA::PTE::Mask Addr Mask Definition: pagetable.hh:50 MipsISA::PTE::serialize void serialize(CheckpointOut &cp) const Definition: pagetable.cc:42 fatal #define fatal(...) Definition: misc.hh:163 BaseTLB::Execute Definition: tlb.hh:61 MipsISA::TLB::nextnlu void nextnlu() Definition: tlb.hh:67 MipsISA::TLB::translateData Fault translateData(RequestPtr req, ThreadContext *tc, bool write) Definition: tlb.cc:300 faults.hh MipsISA::i Bitfield< 2 > i Definition: pra_constants.hh:278 MipsISA::PTE::asid uint8_t asid Definition: pagetable.hh:52 MipsISA::TLB::~TLB virtual ~TLB() Definition: tlb.cc:71 MipsISA::TLB::translateFunctional Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode) Function stub for CheckerCPU compilation issues. Definition: tlb.cc:332 Addr uint64_t Addr Address type This will probably be moved somewhere else in the near future. Definition: types.hh:142 inifile.hh Declaration of IniFile object. CheckpointIn Definition: serialize.hh:340 MipsISA::PTE::unserialize void unserialize(CheckpointIn &cp) Definition: pagetable.cc:61 Process::pTable PageTableBase * pTable Definition: process.hh:178 MipsISA::TLB::read_misses Stats::Scalar read_misses Definition: tlb.hh:71 SERIALIZE_SCALAR #define SERIALIZE_SCALAR(scalar) Definition: serialize.hh:143 pra_constants.hh MipsISA::TLB::Params MipsTLBParams Params Definition: tlb.hh:83 BaseTLB::Mode Mode Definition: tlb.hh:61 Stats::DataWrap::name Derived & name(const std::string &name) Set the name and marks this stat to print at the end of simulation. Definition: statistics.hh:254 X86ISA::size int size() Definition: pagetable.hh:146 SimObject::name virtual const std::string name() const Definition: sim_object.hh:117 MipsISA::TLB Definition: tlb.hh:57 page_table.hh Declarations of a non-full system Page Table. CheckpointOut std::ostream CheckpointOut Definition: serialize.hh:67 MipsISA::PTE::C1 uint8_t C1 Definition: pagetable.hh:66 BaseTLB::Translation Definition: tlb.hh:89 MipsISA::TLB::unserialize void unserialize(CheckpointIn &cp) override Unserialize an object. Definition: tlb.cc:213 Request::getVaddr Addr getVaddr() const Definition: request.hh:616 MipsISA::mode Bitfield< 11, 7 > mode Definition: dt_constants.hh:97 MipsISA::TLB::read_accesses Stats::Scalar read_accesses Definition: tlb.hh:73 MipsISA::TLB::checkCacheability static Fault checkCacheability(RequestPtr &req) Definition: tlb.cc:145 Request::STRICT_ORDER The request is required to be strictly ordered by CPU models and is non-speculative. Definition: request.hh:124 MipsISA::TLB::translateInst Fault translateInst(RequestPtr req, ThreadContext *tc) Definition: tlb.cc:285 MipsISA::TLB::insertAt void insertAt(MipsISA::PTE &pte, unsigned Index, int _smallPages) Definition: tlb.cc:158 Process Definition: process.hh:63 MipsISA::TLB::finalizePhysical Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const Definition: tlb.cc:339 Stats::DataWrap::desc Derived & desc(const std::string &_desc) Set the description and marks this stat to print at the end of simulation. Definition: statistics.hh:287 MipsISA::TLB::translateTiming void translateTiming(RequestPtr req, ThreadContext *tc, Translation *translation, Mode mode) Definition: tlb.cc:324 MipsISA::TLB::lookupTable PageTable lookupTable Definition: tlb.hh:61 Serializable::ScopedCheckpointSection Scoped checkpoint section helper class. Definition: serialize.hh:240 MipsISA::TLB::write_accesses Stats::Scalar write_accesses Definition: tlb.hh:77 MipsISA::p Bitfield< 0 > p Definition: pra_constants.hh:325 BaseTLB::Translation::finish virtual void finish(const Fault &fault, RequestPtr req, ThreadContext *tc, Mode mode)=0 Request::setFlags void setFlags(Flags flags) Note that unlike other accessors, this function sets specific flags (ORs them in); it does not assign... Definition: request.hh:595 Fault std::shared_ptr< FaultBase > Fault Definition: types.hh:184 MipsISA::TLB::accesses Stats::Formula accesses Definition: tlb.hh:80 MipsISA::TLB::misses Stats::Formula misses Definition: tlb.hh:79 MipsISA::TLB::insert void insert(Addr vaddr, MipsISA::PTE &pte) Definition: tlb.cc:186 MipsISA::TLB::smallPages int smallPages Definition: tlb.hh:92 MipsISA::PTE::C0 uint8_t C0 Definition: pagetable.hh:60 MipsISA::PTE::D0 bool D0 Definition: pagetable.hh:58 Generated on Fri Jun 9 2017 13:03:36 for gem5 by doxygen 1.8.6
